M38D59GCHP#U0 Renesas Electronics America, M38D59GCHP#U0 Datasheet
M38D59GCHP#U0
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M38D59GCHP#U0 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The 38D5 Group is the 8-bit microcomputer based on the 740 Family core technology. The 38D5 Group is pin-compatible with the 38C5 Group. The 38D5 Group has an LCD drive control circuit, an ...
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Group PIN CONFIGURATION (TOP VIEW /( RDY2 /( CLK2 /( OUT2 /( IN2 ...
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Group PIN CONFIGURATION (TOP VIEW) P2 /SEG /( /SEG /( /( RDY2 /( CLK2 ...
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Group Table 1 Performance overview (1) Parameter Number of basic instructions Instruction execution time Oscillation frequency Memory sizes ROM (QzROM version) RAM Memory sizes ROM (Flash memory version) RAM Input port I/O port P0-P6, ...
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Group Table 2 Performance overview (2) Parameter Power dissipation In frequency/2 mode (QzROM version) In low-speed mode Power dissipation In frequency/2 mode (Flash memory version) In low-speed mode Input/Output characteristics Input/Output withstand voltage Output current Operating temperature range Device ...
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Group Fig. 3 Functional block diagram Rev.3.04 May 20, 2008 Page 6 of 134 REJ03B0158-0304 ...
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Group PIN DESCRIPTION Table 3 Pin description (1) Pin Name Power source CC SS Reset input RESET X Clock input IN X Clock output OUT LCD power L1, L2, L3 source − COM ...
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Group Table 4 Pin description (2) Pin Name P5 /AN /RTP I/O port /AN /RTP − /AN /ADKEY ...
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Group PART NUMBERING Product M38D5 XXX FP Fig. 4 Part numbering Rev.3.04 May 20, 2008 Page 9 of 134 REJ03B0158-0304 Package type FP: PRQP0080GB-A package HP: PLQP0080KB-A package ROM number Omitted in the shipped in ...
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Group GROUP EXPANSION Renesas plans to expand the 38D5 Group as follows. Memory Size <QzROM version> • ROM size ................................................... bytes • RAM size .................................................. 1536 to 2048 bytes <Flash memory version> • ROM ...
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Group Table 6 Differences between QzROM and flash memory versions Oscillation circuit at reset and at returning from stop mode Termination of OSCEL/CNV pin SS Main clock oscillation at reset and at returning from stop mode On-chip oscillator oscillation ...
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Group FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The 38D5 Group uses the standard 740 Family instruction set. Refer to the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST ...
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Group ← M(S) (PC H Push return address on stack (S) − 1 ← (S) ← M(S) (PC L (S) − 1 ← (S) Subroutine Execute RTS ← (S) ( POP return address from stack ← (PC ...
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Group [Processor Status Register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be ...
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Group [CPU Mode Register (CPUM)] 003B The CPU mode register contains the stack page selection bit, etc. This register is allocated at address 003B After the system is released from reset, the mode depends on the OSCSEL pin state ...
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Group Reset OSCSEL ? H L After releasing reset N Low-speed/X mode ? IN Y Start the oscillation (bits 4 and 5 of CPUM) Wait by on-chip oscillator operation until establishment of oscillator clock Select internal system clock (bit ...
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Group MEMORY • Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. • RAM RAM is used for data storage and for stack area of ...
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Group RAM area RAM size Address (bytes) XXXX 192 00FF 256 013F 384 01BF 512 023F 640 02BF 768 033F 896 03BF 1024 043F 1536 063F 2048 083F ROM area ROM size Address (bytes) YYYY 4096 F000 16 8192 ...
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Group Port P0 (P0) 0000 16 Port P0 direction register (P0D) 0001 16 Port P1 (P1) 0002 16 Port P1 direction register (P1D) 0003 16 Port P2 (P2) 0004 16 Port P2 direction register (P2D) 0005 16 Port P3 ...
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Group I/O PORTS • Direction Registers (Ports P0-P6, P7 The I/O ports P0-P6, P7 -P7 have direction registers which 2 4 determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, ...
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Group Table 9 List of I/O port function Pin Name Input/Output − P0 /SEG Port P0 Input/Output /SEG individual bits 7 15 − P1 /SEG Port P1 Input/Output /SEG individual bits 7 23 ...
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Group (1) Ports P0, P1 Segment data Segment output disable bit Direction register Data bus Port latch (3) Port P4 0 Serial I/O enable bit Receive enable bit Direction register Data bus Port ...
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Group (7) Port P4 4 Direction register Data bus Port latch Serial I/O2 input Key-on wakeup interrupt input (9) Port P4 6 Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Direction register Data bus Port latch ...
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Group (13) Port P5 7 Direction register Data bus Port latch ADKEY selection bit ADKEY enable bit Analog input pin selection bit A/D conversion input (15) Port P6 1 Port Xc switch bit Port Xc switch bit Direction register ...
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Group (19) Port P6 6 Direction register Data bus Port latch CNTR interrupt input 0 INT interrupt input 1 INT (21) Ports Direction register Data bus Port latch Port/Timer output selected Timer output/PWM ...
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Group • Termination of unused pins • Termination of common pins I/O ports: Select an input port or an output port and follow each processing method. In addition recommended that related registers be overwritten periodically to prevent ...
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Group Table 10 Termination of unused pins Pin Termination 1 −P0 P0 /SEG /SEG I/O port −P1 P1 /SEG /SEG /SEG /(KW )− /SEG 7 7 ...
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Group INTERRUPTS The 38D5 Group interrupts are vector interrupts with a fixed priority scheme, and generated by 16 sources among 17 sources: 6 external, 10 internal, and 1 software. The interrupt sources, vector addresses are shown in Table 11. ...
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Group Interrupt request bit Interrupt enable bit Interrupt disable flag (I) Fig. 18 Interrupt control • Interrupt Disable Flag The interrupt disable flag is assigned to bit 2 of the processor status register. This flag controls the acceptance of ...
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Group b7 b0 Interrupt edge selection register (INTEDGE : address 003A INT interrupt edge selection bit 0 INT interrupt edge selection bit 1 INT interrupt edge selection bit 2 Timer Y/CNTR 0 : Timer Y interrupt 1 : CNTR ...
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Group • Interrupt Request Generation, Acceptance, and Handling Interrupts have the following three phases. (i) Interrupt Request Generation An interrupt request is generated by an interrupt source (external interrupt signal input, timer underflow, etc.) and the corresponding request bit ...
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Group <Notes> The interrupt request bit may be set to “1” in the following cases. • When setting the external interrupt active edge Related bits: INT interrupt edge selection bit 0 (bit 0 of interrupt edge selection register (address ...
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Group • Key Input Interrupt (Key-on Wake-Up) A key input interrupt request is generated by detecting the falling −P2 edge from any pin of ports input mode. In other words generated ...
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Group A key input interrupt is controlled by the key input control register and port direction registers. When the key input interrupt is enabled, set “1” to the key input control register. A key input −P2 −P4 of any ...
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Group TIMERS 8-Bit Timer The 38D5 Group has four built-in 8-bit timers: Timer 1, Timer 2, Timer 3, and Timer 4. (1) φ SOURCE Frequency divider The following values can be selected the clock for Timer; 1/1, 1/2, 1/16, ...
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Group • Frequency Divider For Timer Timer 1, timer 2, timer 3 and timer 4 have the frequency divider for the count source. The count source of the frequency divider is switched the ...
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Group b7 b0 Timer 12 mode register (T12M: address 0025 Timer 1 count stop bit 0 : Count operation 1 : Count stop Timer 2 count stop bit 0 : Count operation 1 : Count stop Timer 1 count ...
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Group 16-bit Timer Read and write operation on 16-bit timer must be performed for both high and low-order bytes. When reading a 16-bit timer, read the high-order byte first. When writing to a 16-bit timer, write the low-order byte ...
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Group • Frequency Divider For Timer Each timer X and timer Y have the frequency dividers for the count source. The count source of the frequency divider is switched the on-chip oscillator OCO ...
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Group t s Timer X count source Timer X PWM mode IGBT output mode T output XOUT1 (TXCON1 bit 5 = “0”) T output XOUT2 (TXCON2 bit 1 = “0”) The following PWM waveform is output; Duty of T ...
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Group (4) Set of Timer X Mode Register Set the write control bit of the timer X mode register to “1” (write to the latch only) when setting the IGBT output and PWM modes. Output waveform simultaneously reflects the ...
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Group 2 (1) φSOURCE Frequency divider Timer Y dividing frequency selection bit “0” “1” Count source selection bit CNTR active 1 edge switch bit “0” CNTR 1 “1” Real time port 2 control bit “1” P5 /RTP ...
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Group <Notes on Timer Y> • CNTR Interrupt Active Edge Selection 1 CNTR interrupt active edge depends on the CNTR 1 switch bit. However, in pulse width HL continuously measurement mode, CNTR interrupt request is generated at 1 both ...
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Group SERIAL INTERFACE • SERIAL I/O1 Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation CLK1 ...
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Group (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by setting the serial I/O mode selection bit of the serial I/O1 control register to “0”. Eight serial data transfer formats can be ...
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Group [Transmit Buffer Register/Receive Buffer Register (TB1/RB1)] The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and the receive buffer is read-only character bit length is ...
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Group Serial I/O1 status register b7 b0 (SIO1STS : address 0019 Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: ...
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Group • Serial I/O2 The serial I/O2 function can be used only for clock synchronous serial I/O. For serial I/O2, the transmitter and the receiver must use the same clock. When the internal clock is selected as the operating ...
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Group [Serial I/O2 Operation] Writing to the serial I/O2 register initializes the serial I/O2 counter to “7”. After writing, the S pin outputs data each time the OUT2 synchronous clock changes from “H” to “L”. The S captures data ...
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Group A/D CONVERTER The 38D5 Group has a 10-bit A/D converter. The A/D converter performs successive approximation conversion. The 38D5 Group has the ADKEY function which perform A/D conversion of the “L” level analog input from the ADKEY pin ...
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Group control register (ADCON: address 0015 Analog input pin selection bits ...
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Group LCD DRIVE CONTROL CIRCUIT The 38D5 Group has the built-in Liquid Crystal Display (LCD) drive control circuit consisting of the following. • LCD display RAM • Segment output disable register • LCD mode register • Selector • Timing ...
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Group Fig. 44 Block diagram of LCD controller/driver Rev.3.04 May 20, 2008 Page 53 of 134 REJ03B0158-0304 ...
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Group • Voltage Multiplier The voltage multiplier performs threefold boosting. This circuit inputs a reference voltage for boosting from LCD power input pin V . Set each bit of the segment output disable registers and L1 the LCD mode ...
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Group • LCD Display RAM The 36-byte area of address 0840 to 0863 16 RAM for the LCD display. When “1” is written to these addresses, the corresponding segments of the LCD display panel are turned on. The LCDCK ...
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Group Internal signal LCDCK timing 1/8 duty COM 0 COM 1 COM 2 COM 3 COM 4 COM 5 COM 6 COM 7 SEG 0 OFF ON COM COM COM COM 1/4 duty COM 0 COM ...
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Group Internal signal LCDCK timing 1/8 duty COM 0 COM 1 COM 2 COM 3 COM 4 COM 5 COM 6 COM 7 SEG 0 OFF ON COM COM COM COM 1/4 duty COM 0 COM ...
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Group ROM CORRECTION FUNCTION A part of program in ROM can be corrected. Set the start address of the corrected ROM data (i. code address of the beginning instruction) to the ROM correction address high-order and low-order ...
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Group WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit counter. ...
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Group CLOCK OUTPUT FUNCTION A system clock φ can be output from I/O port P7 function of I/O port, timer 2 output function and system clock φ output function are controlled by the clock output control register (address 0FF3 ...
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Group RESET CIRCUIT To reset the microcomputer, RESET pin should be held at an “L” level for 2 µs or more. Then the RESET pin is returned to an “H” level (the power source voltage should be between V ...
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Group Address 0000 (1) Port P0 0001 (2) Port P0 direction register 0002 (3) Port P1 0003 (4) Port P1 direction register Port P2 0004 (5) 0005 (6) Port P2 direction register 0006 (7) Port P3 0007 (8) Port ...
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Group CLOCK GENERATING CIRCUIT The oscillation circuit of 38D5 Group can be formed by connecting an oscillator, capacitor and resistor between and supply a clock signal externally, OUT CIN COUT input it to ...
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Group • Oscillation Control (1) Stop Mode If the STP instruction is executed, the system clock φ stops at an “H” level, and main clock and sub-clock oscillators stop. In this time, values set previously to timer 1 latch ...
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Group CPUM2 BIT0 On-chip oscillator stop bit “0” On-chip oscillator OUT ( OUT oscillation stop bit CPUM BIT5 X X COUT CIN STP instruction Reset Interrupt disable flag I Interrupt ...
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Group On-chip oscillator mode X stop IN X stop CIN OCO oscillation φ =f(OCO)/32 CM4 CM5 X oscillation IN • ...
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Group QzROM Writing Mode In the QzROM writing mode, the user ROM area can be rewritten while the microcomputer is mounted on-board by using a serial programmer which is applicable for this microcomputer. Table 15 lists the pin description ...
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Group RDY2 /( CLK2 /( OUT2 /( IN2 0 68 ESPGMB RDY1 ...
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Group P2 /SEG /( /SEG /( /( RDY2 /( CLK2 /( OUT2 ...
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Group Vcc ∗ : Open-collector buffer 1 Note : For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF. ...
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Group Vcc Open-collector buffer When programming 38D5 Group is performed, disconnect Vcc from OSCSEL by a jumper switch. 2 Note ...
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Group T_VDD T_VPP T_TXD T_RXD T_SCLK T_BUSY T_PGM/OE/MD RESET circuit T_RESET GND Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF. Fig. 68 When using programmer of Suisei Electronics System Co., ...
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Group T_VDD T_VPP T_TXD T_RXD T_SCLK T_BUSY T_PGM/OE/MD RESET circuit T_RESET GND * When programming QzROM is performed, disconnect Vcc from OSCSEL by a jumper switch Note: For the programming circuit, the wiring capacity of each signal ...
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Group FLASH MEMORY MODE The 38D5 Group flash memory version has the flash memory that can be rewritten with a single power source. For this flash memory, three flash memory modes are available in which to read, program, and ...
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Group Boot Mode The control program for CPU rewrite mode must be written into the User ROM or Boot ROM area in parallel I/O mode beforehand. (If the control program is written into the Boot ROM area, the standard ...
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Group Outline Performance CPU rewrite mode is usable in the single-chip or Boot mode. The only User ROM area can be rewritten. In CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by ...
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Group b7 b0 Flash memory control register 2 (FMCR2: address : 0FE2 Not used (return “1” when read) Not used (do not write “1” to this bit.) Not used (return “1” when read) Not used (return “0” when read) ...
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Group <Notes on CPU Rewrite Mode> Take the notes described below when rewriting the flash memory in CPU rewrite mode. (1) Operation speed During CPU rewrite mode, set the system clock φ to 4.0 MHz or less using the ...
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Group Software Commands Table 18 lists the software commands. After setting the CPU rewrite mode select bit to “1”, execute a software command to specify an erase or program operation. Each software command is explained below. • Read Array ...
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Group • Block Erase Command (20 / writing the command code “20 ” in the first bus cycle and 16 the confirmation command code “D0 16 the second bus cycle that follows, the block erase (erase and ...
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Group • Status Register The status register shows the operating status of the flash memory and whether erase operations and programs ended successfully or in error. It can be read in the following ways: (1) By reading an arbitrary ...
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Group Full Status Check By performing full status check possible to know the execution results of erase and program operations. Figure 77 shows a full status check flowchart and the action to be taken when each error ...
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Group Functions To Inhibit Rewriting Flash Memory Version To prevent the contents of internal flash memory from being read out or rewritten easily, this MCU incorporates a ROM code protect function for use in parallel I/O mode and an ...
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Group • ID Code Check Function Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the programmer is compared with the ID code written in ...
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Group Parallel I/O Mode The parallel I/O mode is used to input/output software commands, address and data in parallel for operation (read, program and erase) to internal flash memory. • User ROM and Boot ROM Areas In parallel I/O ...
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Group Standard serial I/O Mode The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is clock synchronized serial. This mode requires ...
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Group Table 20 Description of pin function (Flash Memory Standard Serial I/O Mode 1) Pin name Signal name V ,V Power supply CC SS CNV CNV SS SS Reset input RESET X Clock input IN X Clock output OUT ...
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Group P4 /S /(KW 7 RDY2 P4 /S /(KW 6 CLK2 P4 /S /(KW 5 OUT2 P4 /S /(KW 4 IN2 BUSY RDY1 SCLK CLK1 P4 /T TXD RXD 0 ...
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Group P2 /SEG /SEG RDY2 CLK2 OUT2 P4 /S /(KW0) 4 IN2 P4 /S BUSY 3 “L”INPUT P4 2 TXD P4 P4 RXD P5 /AN ...
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Group T_VDD T_VPP T_RXD T_TXD T_SCLK T_PGM/OE/MD T_BUSY RESET circuit T_RESET GND Note 1: For the programmer circuit, the wiring capacity of each signal pin must not exceed 47pF. Fig 82. When using programmer (in standard serial I/O mode ...
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Group Vcc ∗ Open-collector buffer 1: Note 1: For the programmer circuit, the wiring capacity of each signal pin must not exceed 47pF. Fig 83. ...
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Group Power source RESET CNV CLK P4 (BUSY Limits Symbol Min. Typ. td(CNV -RESET td(P4 -RESET Fig 84. ...
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Group NOTES ON USE Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. After a reset, initialize flags which affect program execution. ...
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Group NOTES ON QzROM VERSION Wiring to OSCSEL pin 1. OSCSEL = L Connect the OSCSEL pin the shortest possible to the GND pattern which is supplied to the addition connecting an approximately 5 k Ω ...
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Group NOTES ON FLASH MEMORY VERSION CPU Rewrite Mode (1) Operation speed During CPU rewrite mode, set the system clock less using the main clock division ratio selection bits (bits 6 and 7 of address 003B ). 16 (2) ...
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Group Countermeasures against noise (1) Shortest wiring length 1. Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the ...
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Group (3) Oscillator concerns In order to obtain the stabilized operation clock on the user system and its condition, contact the oscillator manufacturer and select the oscillator and oscillation circuit constants. Be careful especially when range of voltage and ...
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Group QzROM VERSION ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Table 22 Absolute maximum ratings Symbol V Power source voltage CC V Input voltage I − P0 − − P4 − ...
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Group Recommended Operating Conditions Table 23 Recommended operating conditions ( 1 Symbol V Power source Frequency/2 mode CC (1) voltage Frequency/4 mode Frequency/8 mode Low-speed mode On-chip oscillator mode When start ...
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Group Table 24 Recommended operating conditions ( 1 Symbol Parameter Σ “H” total peak output current IOH(peak) − P0 − Σ ...
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Group Table 25 Recommended operating conditions ( 1 Symbol Parameter f(CNTR ) Timer X and Timer Y 0 f(CNTR ) Input frequency (duty cycle 50%) 1 f(Tclk) Timer X, Timer Y, ...
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Group Electrical Characteristics Table 26 Electrical characteristics ( 1 Symbol Parameter V “H” output voltage OH − P0 − − ...
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Group Table 27 Electrical characteristics (2) (Vcc = 1 − ° C, f(X stopped, unless otherwise noted) Symbol Parameter V RAM hold voltage When clock is stopped RAM I Power source ...
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Group Table 29 A/D converter characteristics (Vcc = 2 − ° C, output transistors in cut-off state, low-speed included, unless otherwise noted) Symbol Parameter − Resolution ABS Absolute accuracy 10bitAD (quantification ...
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Group Timing Requirements And Switching Characteristics Table 30 Timing requirements (1) (Vcc = 4.0 to 5.5 V, Vss = − ° C, unless otherwise noted) Symbol t (RESET) Reset input “L” pulse ...
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Group Table 31 Timing requirements ( 1 Symbol t (RESET) Reset input “L” pulse width Main clock input cycle time input) IN Main clock ...
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Group Table 32 Switching characteristics (1) (Vcc = 4.0 to 5.5 V, Vss = − ° C, unless otherwise noted) Symbol Serial I/O1 clock output “H” pulse width WH ...
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Group CNTR CNTR 0, 1 INT INT 00, 01 INT INT 10, 11 INT 2 RESET CLK1 S CLK2 IN2 OUT2 Fig 96. Timing diagram Rev.3.04 May 20, ...
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Group FLASH MEMORY VERSION ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Table 34 Absolute maximum ratings Symbol Parameter V Power source voltage CC V Input voltage I − − − ...
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Group Recommended Operating Conditions Table 35 Recommended operating conditions ( 2 Symbol V Power source Frequency/2 mode CC (1) voltage Frequency/4 mode Frequency/8 mode Low-speed mode On-chip oscillator mode V Power ...
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Group Table 36 Recommended operating conditions ( 2 Symbol Σ “H” total peak output current OH(peak) − P0 − Σ ...
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Group Table 37 Recommended operating conditions ( 2 Symbol Parameter f(CNTR ) Timer X and Timer Y 0 f(CNTR ) Input frequency (duty cycle 50%) 1 f(Tclk) Timer X, Timer Y, ...
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Group Electrical Characteristics Table 38 Electrical characteristics ( 2 Symbol Parameter V “H” output voltage OH − P0 − − P3 ...
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Group Table 39 Electrical characteristics (2) (Vcc = 2 A/D converter stopped, unless otherwise noted) Symbol Parameter V RAM hold voltage When clock is stopped RAM I Power source current Frequency/2 mode Vcc=5.0V CC ...
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Group Table 41 A/D converter characteristics (Vcc = 2 − ° C, output transistors in cut-off state, low-speed included, unless otherwise noted) Symbol Parameter − Resolution ABS Absolute accuracy 10bitAD (quantification ...
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Group Timing Requirements And Switching Characteristics Table 42 Power supply circuit characteristics (Vcc = 2.7 to 5.5 V, Vss = − ° C, unless otherwise noted) Symbol Parameter td(P-R) Internal power source ...
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Group Table 44 Timing requirements ( 2 Symbol t (RESET) Reset input “L” pulse width Main clock input cycle time input ...
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Group Table 45 Switching characteristics (1) (Vcc = 4.0 to 5.5 V, Vss = − ° C, unless otherwise noted) Symbol Serial I/O1 clock output “H” pulse width WH ...
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Group CNTR , CNTR 0 1 INT ,INT 01 00 INT ,INT 10 11 INT 2 RESET CLK1 S CLK2 IN2 OUT2 Fig 98. Timing diagram (in ...
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Group PACKAGE OUTLINE Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of the Renesas Technology website. JEITA Package Code RENESAS Code P-QFP80-14x20-0.80 PRQP0080GB ...
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Group JEITA Package Code RENESAS Code P-LQFP80-12x12-0.50 PLQP0080KB Index mark y e Rev.3.04 May 20, 2008 Page 121 of 134 REJ03B0158-0304 Previous Code MASS[Typ.] 80P6Q-A 0. Terminal ...
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Group APPENDIX Note on Programming 1. Processor Status Register (1) Initialization of the processor status register It is required to initialize the processor status register (PS) flags which affect program execution particularly essential to initialize the T ...
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Group 3. JMP Instruction When using the JMP instruction (indirect addressing mode), do not specify the address where “FF 16 order 8 bits as the operand. 4. Multiplication and Division Instructions (1) The MUL and DIV instructions are not ...
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Group 3. Direction Registers The values of the port direction registers cannot be read. This means impossible to use the LDA instruction, memory operation instruction when the T flag is “1”, addressing mode using direction register values ...
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Group Notes on Interrupts 1. Changing Related Register Settings If the interrupt occurrence synchronized with the following settings is not required, take the sequence shown below. • When selecting the external interrupt active edge • When selecting the interrupt ...
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Group Notes on Timers 1. Frequency Divider All timers shares one circuit for the frequency divider to generate the count source. Thus the frequency divider is not initialized when each individual timer is activated. When the frequency divider is ...
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Group 10. Write to Timer X (1) Timer X can select either writing data to both the latch and the timer at the same time or writing data only by the timer X write control bit (b3) in the ...
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Group Notes on Serial I/O1 1. Write to Baud Rate Generator Write to the baud rate generator while transmission/reception is stopped. 2. Setting Sequence When Serial I/O1 Transmit Interrupt Used To use the serial I/O1 transmit interrupt, if the ...
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Group Notes on A/D Conversion 1. Analog Input Pin Set the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01 µ µ addition, operations ...
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Group Notes on LCD Drive Control Circuit 1. Multiplier Circuit When the multiplier circuit is used, set the multiplier circuit control bit to “1” (multiplier circuit enabled) after applying a voltage from 1 more to 2.1 V ...
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Group 3. Executing STP Instruction Executing the STP instruction sets the LCD enable bit (bit 4 of LCD mode register1 (address 0013 )) to “0” and the LCD panel 16 turns off. To turn the LCD panel on after ...
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Group Notes on Flash Memory Mode • CPU Rewrite Mode (1) Operating Speed During CPU rewrite mode, set the system clock φ to 4.0 MHz or less using the main clock division ratio selection bits (bits 6 and 7 ...
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Group Notes on QzROM Version Wiring to OSCSEL pin (1) OSCSEL = L Connect the OSCSEL pin the shortest possible to the GND pattern which is supplied to the V pin of the microcomputer addition connecting an ...
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Group Notes on Flash Memory Version CPU Rewrite Mode 1. Operating Speed During CPU rewrite mode, set the system clock less using the main clock division ratio selection bits (bits 6 and 7 of address 003B ). 16 2. ...
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REVISION HISTORY REVISION HISTORY Rev. Date Page − 1.00 Aug 12, 2005 − 2.00 Jan 23, 2006 − − − 61- 38D5 Group Data ...
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REVISION HISTORY Rev. Date Page 2.00 Jan 23, 2006 2.01 Mar 24, 2006 2.02 Jul 10, 2006 ...
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REVISION HISTORY Rev. Date Page 2.03 Aug 31, 2006 75 76 2.04 Feb 02, 2007 13 43 ...
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REVISION HISTORY Rev. Date Page 2.04 Feb 02, 2007 81 − 3.01 Aug 08, 2007 ...
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REVISION HISTORY Rev. Date Page 3.01 Aug 08, 2007 69 38D5 ...
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REVISION HISTORY Rev. Date Page 3.01 Aug 08, 2007 97, 108 98-106 98 101 103 104, 115 Table 31 and 45: Each main clock input condition (V 105 108 112 113 113, 114 Table 41, 42, and 43: V 114 ...
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REVISION HISTORY Rev. Date Page 3.04 May 20 2008 21” 94, 133 All trademarks and registered trademarks are the property of their respective owners. 38D5 Group Data Sheet Description )” → “P4 Table 9: ...
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Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained ...