M38D59GCHP#U0 Renesas Electronics America, M38D59GCHP#U0 Datasheet - Page 22

• Manufacturer Part Number: M38D59GCHP#U0
• Description: IC 740/38D5 MCU QZ-ROM 80LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38D59GCHP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: LCD, LED, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: QzROM
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

38D5 Group
Rev.3.04
REJ03B0158-0304
I/O PORTS
• Direction Registers (Ports P0-P6, P7
The I/O ports P0-P6, P7
determine the input/output direction of each individual pin. Each
bit in a direction register corresponds to one pin, each pin can be
set to be input port or output port.
When “0” is written to the bit of the direction register, the
corresponding pin becomes an input pin. As for ports P0−P3,
when “1” is written to the bit of the direction register and the
segment output disable register, the corresponding pin becomes
an output pin. As for ports P4−P6, P7
the bit of the direction register, the corresponding pin becomes
an output pin.
If data is read from a pin set to output, the value of the port latch
is read, not the value of the pin itself. However, when peripheral
output (RTP
T
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
• Ports P7
These are input ports which are shared with the voltage
multiplier. When these are read out at using the voltage
multiplier, the contents are “1”.
• Pull-up Control
Each individual bit of ports P0−P3 can be pulled up with a
program by setting direction registers and segment output disable
registers 0 to 2 (addresses 0FF4
The pin is pulled up by setting “0” to the direction register and
“1” to the segment output disable register.
By setting the PULL registers (addresses 0FF0
ports P4−P7 can control pull-up with a program.
However, the contents of PULL register do not affect ports
programmed as the output ports.
Fig. 12 Structure of ports P0 to P3
2OUT
Segment output
Direction
register
disable register
/CKOUT) is selected, the output value is read. Pins set to
“0”
“1”
0
, P7
1
May 20, 2008 Page 20 of 134
, RTP
1
Input port
No pull-up
Segment
output
0
“0”
, T
XOUT1
2
-P7
4
16
Port output
have direction registers which
Input port
Pull-up
, T
to 0FF6
XOUT2
“1”
2
-P7
4
16
, T
when “1” is written to
).
2
-P7
4OUT
4
16
Initial state
)
, T
to OFF2
3OUT
and
16
),
Fig. 13 Structure of PULL register and segment output
Note1: The PULL register and segment output disable register affect only ports
b7
b7
b7
b7
b7
b7
programmed as the input ports.
disable register
b0
b0
b0
b0
b0
b0
PULL register 2
(PULL2 : address 0FF1
PULL register 3
(PULL3 : address 0FF2
Segment output disable register 0
(SEG0 : address 0FF4
Segment output disable register 1
(SEG1 : address 0FF5
PULL register 1
(PULL1 : address 0FF0
Segment output disable register 2
(SEG2 : address 0FF6
P5
P5
P5
P5
P5
P5
P5
P5
P6
P6
P6
P6
P6
P6
P6
P6
P4
P4
P7
Not used (do not write “1”)
Not used (return “0” when read)
P0
P0
P0
P0
P0
P0
P0
P0
P2
P2
P2
P2
P2
P2
P2
P2
P1
P1
P3
P3
Not used (do not write “1”)
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0-
4-
2-
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0-
4-
0-
4-
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
P4
P4
P7
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
P1
P1
P3
P3
3
7
4
3
7
3
7
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
16
16
16
16
16
16
)
)
)
))
))
)
0 : No pull-up
1 : Pull-up
0 : No pull-up
1 : Pull-up
0 : No pull-up
1 : Pull-up
0 : No pull-up
1 : Pull-up
0 : No pull-up
1 : Pull-up
0 : No pull-up
1 : Pull-up