M38D59GCHP#U0 Renesas Electronics America, M38D59GCHP#U0 Datasheet - Page 48

IC 740/38D5 MCU QZ-ROM 80LQFP

M38D59GCHP#U0

Manufacturer Part Number
M38D59GCHP#U0
Description
IC 740/38D5 MCU QZ-ROM 80LQFP
Manufacturer
Renesas Electronics America
Series
740/38000r
Datasheet

Specifications of M38D59GCHP#U0

Core Processor
740
Core Size
8-Bit
Speed
12.5MHz
Connectivity
SIO, UART/USART
Peripherals
LCD, LED, PWM, WDT
Number Of I /o
59
Program Memory Size
48KB (48K x 8)
Program Memory Type
QzROM
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
80-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M38D59GCHP#U0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
38D5 Group
Rev.3.04
REJ03B0158-0304
[Transmit Buffer Register/Receive Buffer Register
(TB1/RB1)]
The transmit buffer register and the receive buffer register are
located at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits,
the MSB of data stored in the receive buffer is “0”.
[Serial I/O1 Status Register (SIO1STS)]
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is set to “0” when the receive
buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer
register, and the receive buffer full flag is set. A write to the
serial I/O1 status register sets all the error flags OE, PE, FE, and
SE (bit 3 to bit 6, respectively) to “0”. Writing “0” to the serial
I/O1 enable bit SIOE (bit 7 of the serial I/O1 control register)
also sets all the status flags to “0”, including the error flags.
All bits of the serial I/O1 status register are set to “0” at reset, but
if the transmit enable bit (bit 4) of the serial I/O1 control register
has been set to “1”, the transmit shift completion flag (bit 2) and
the transmit buffer empty flag (bit 0) become “1”.
[Serial I/O1 Control Register (SIO1CON)]
The serial I/O1 control register consists of eight control bits for
the serial I/O1 function.
[UART Control Register (UARTCON)]
The UART control register consists of four control bits (bits 0 to
3) which are valid when asynchronous serial I/O is selected and
set the data format of the data transfer and one bit (bit 4) which is
always valid and sets the output structure of the P4
[Baud Rate Generator (BRG)]
The baud rate generator determines the baud rate for serial
transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate
generator.
May 20, 2008 Page 46 of 134
1
/T
X
D pin.
<Notes on serial I/O1>
When setting transmit enable bit of serial I/O1 to “1”, the serial
I/O1 transmit interrupt request bit is automatically set to “1”.
When not requiring the interrupt occurrence synchronous with
the transmission enabled, take the following sequence.
(1) Set the serial I/O1 transmit interrupt enable bit to “0”
(2) Set the transmit enable bit to “1”.
(3) Set the serial I/O1 transmit interrupt request bit to “0” after
(4) Set the serial I/O1 transmit interrupt enable bit to “1”
(disabled).
1 or more instructions have been executed.
(enabled).

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