M38D59GCHP#U0 Renesas Electronics America, M38D59GCHP#U0 Datasheet - Page 64

• Manufacturer Part Number: M38D59GCHP#U0
• Description: IC 740/38D5 MCU QZ-ROM 80LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38D59GCHP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: LCD, LED, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: QzROM
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

38D5 Group
Rev.3.04
REJ03B0158-0304
Fig. 59 Internal status at reset
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
(34)
(35)
Port P0
Port P0 direction register
Port P1
Port P1 direction register
Port P2
Port P2 direction register
Port P3
Port P3 direction register
Port P4
Port P4 direction register
Port P5
Port P5 direction register
Port P6
Port P6 direction register
Port P7
Port P7 direction register
CPU mode register 2
RRF register
LCD mode register 1
LCD mode register 2
AD control register
Serial I/O1 status register
Serial I/O1 control register
UART control register
Serial I/O2 control register
Timer 1
Timer 2
Timer 3
Timer 4
PWM01 register
Timer 12 mode register
Timer 34 mode register
Timer 1234 mode register
Timer 1234 frequency division
selection register
Watchdog timer control register
May 20, 2008 Page 62 of 134
Address
000A
000B
000C
000D
000E
001A
001B
001D
000F
0000
0001
0002
0003
0004
0005
0006
0007
0008
0009
0011
0012
0013
0014
0015
0019
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
1 0 0 0 0
0 0 0 0 0
1 1 1 0 0
0 0 0 1 1
Register contents
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
FF
FF
FF
00
00
00
08
00
00
01
00
00
00
00
00
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
0
0
0
1
0 0
0 *
0 0
1 1
×: Not fixed
*: Depends on OSCSEL setting at the QzROM version.
Since the initial values for other than above mentioned registers and RAM
contents are indefinite at reset, they must be set.
(36)
(37)
(38)
(39)
(40)
(41)
(42)
(43)
(44)
(45)
(46)
(47)
(48)
(49)
(50)
(51)
(52)
(53)
(54)
(55)
(56)
(57)
(58)
(59)
(60)
(61)
(62)
(63)
(64)
(65)
(66)
(67)
(68)
(69)
(70)
(71)
(72)
In the flash memory version, the CPU mode register 2 (address
0011
set to “E0
Timer X (low-order)
Timer X (high-order)
Timer X (extension)
Timer X mode register
Timer X control register 1
Timer X control register 2
Compare register 1 (low-order)
Compare register 1 (high-order)
Compare register 2 (low-order)
Compare register 2 (high-order)
Compare register 3 (low-order)
Compare register 3 (high-order)
Timer Y (low-order)
Timer Y (high-order)
Timer Y mode register
Timer Y control register
Interrupt edge selection register
CPU mode register
Interrupt request register 1
Interrupt request register 2
Interrupt control register 1
Interrupt control register 2
PULL register 1
PULL register 2
PULL register 3
Clock output control register
Segment output disable register 0
Segment output disable register 1
Segment output disable register 2
Key input control register
ROM correction address 1(high-order)
ROM correction address 1(low-order)
ROM correction address 2 (high-order)
ROM correction address 2 (low-order)
ROM correction enable register
Processor status register
Program counter
16
), is set to “00
16
”.
16
” and the CPU mode register (address 003B
Address
0FFC
002C
002D
003C
003D
0FFA
0FFB
002A
002B
002E
003A
003B
003E
0FF0
0FF1
0FF2
0FF3
0FF4
0FF5
0FF6
0FF7
0FF8
0FF9
002F
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
003F
(PC
(PC
(PS)
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
H
L
)
)
* 1 * 0 0
×
Register contents
× ×
FFFD
FFFC
FF
FF
FF
FF
FF
FF
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0F
00
00
00
00
00
00
16
16
× ×
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
contents
contents
0
1
0 0
16
× ×
) is