M38D59GCHP#U0 Renesas Electronics America, M38D59GCHP#U0 Datasheet - Page 49

• Manufacturer Part Number: M38D59GCHP#U0
• Description: IC 740/38D5 MCU QZ-ROM 80LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38D59GCHP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: LCD, LED, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: QzROM
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

38D5 Group
Rev.3.04
REJ03B0158-0304
Fig. 37 Structure of serial I/O1 related registers
b7
b7
May 20, 2008 Page 47 of 134
b0
b0
Serial I/O1 status register
(SIO1STS : address 0019
UART control register
(UARTCON : address 001B
Character length selection bit (CHAS)
Parity enable bit (PARE)
Parity selection bit (PARS)
Stop bit length selection bit (STPS)
P4
Not used (return “1” when read)
Transmit buffer empty flag (TBE)
Receive buffer full flag (RBF)
Transmit shift completion flag (TSC)
Overrun error flag (OE)
Parity error flag (PE)
Framing error flag (FE)
Summing error flag (SE)
Not used (returns “1” when read)
0: 8 bits
1: 7 bits
0: Parity checking disabled
1: Parity checking enabled
0: Even parity
1: Odd parity
0: 1 stop bit
1: 2 stop bits
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
0: Buffer full
1: Buffer empty
0: Buffer empty
1: Buffer full
0: Transmit shift in progress
1: Transmit shift completed
0: No error
1: Overrun error
0: No error
1: Parity error
0: No error
1: Framing error
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
1
/TXD P-channel output disable bit (POFF)
16
)
16
)
Note1: φSOURCE indicates the followings:
b7
•X
•On-chip oscillator divided by 4 in the on-chip oscillator mode
•Sub-clock in the low-speed mode
IN
input in the frequency/2, 4, or 8 mode
b0
Serial I/O1 control register
(SIO1CON : address 001A
BRG count source selection bit (CSS)
Serial I/O1 synchronous clock selection bit (SCS)
S
Transmit interrupt source selection bit (TIC)
Transmit enable bit (TE)
Receive enable bit (RE)
Serial I/O1 mode selection bit (SIOM)
Serial I/O1 enable bit (SIOE)
0: φSOURCE
1: φSOURCE/4
0: BRG output divided by 4 when clock synchronous
1: External clock input when clock synchronous serial
0: P4
1: P4
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
0: Transmit disabled
1: Transmit enabled
0: Receive disabled
1: Receive enabled
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
0: Serial I/O1 disabled
1: Serial I/O1 enabled
RDY1
serial I/O is selected.
BRG output divided by 16 when UART is selected.
I/O is selected.
External clock input divided by 16 when UART is selected.
(pins P4
(pins P4
3
3
output enable bit (SRDY)
pin operates as ordinary I/O pin
pin operates as S
0
0
to P4
to P4
(1)
3
3
operate as ordinary I/O pins)
operate as serial I/O pins)
16
)
RDY1
output pin