AT91SAM7SE256-AU Atmel, AT91SAM7SE256-AU Datasheet - Page 108
![IC ARM7 MCU FLASH 256K 128-LQFP](/photos/6/71/67112/128-lqfp_sml.jpg)
AT91SAM7SE256-AU
Manufacturer Part Number
AT91SAM7SE256-AU
Description
IC ARM7 MCU FLASH 256K 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT88SC-SDK1.pdf
(90 pages)
2.AT91SAM7SE256-AU.pdf
(673 pages)
3.AT91SAM7SE32-AU.pdf
(655 pages)
Specifications of AT91SAM7SE256-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
55 MHz
Number Of Programmable I/os
88
Number Of Timers
2
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7SE-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Controller Family/series
AT91SAM7xxxxx
No. Of I/o's
88
Ram Memory Size
32KB
Cpu Speed
48MHz
No. Of Timers
3
Rohs Compliant
Yes
For Use With
AT91SAM7SE-EK - EVAL BOARD FOR AT91SAM7SEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7SE256-AU
Manufacturer:
ATMEL
Quantity:
165
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19.2.4.3
108
SAM7SE512/256/32 Preliminary
Lock Bit Protection
Erase All operation is allowed only if there are no lock bits set. Thus, if at least one lock region is
locked, the bit LOCKE in MC_FSR rises and the command is cancelled. If the bit LOCKE has
been written at 1 in MC_FMR, the interrupt line rises.
When programming is complete, the bit FRDY bit in the Flash Programming Status Register
(MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the inter-
rupt line of the Memory Controller is activated.
Two errors can be detected in the MC_FSR register after a programming sequence:
Lock bits are associated with several pages in the embedded Flash memory plane. This defines
lock regions in the embedded Flash memory plane. They prevent writing/erasing protected
pages.
After production, the device may have some embedded Flash lock regions locked. These locked
regions are reserved for a default application. Refer to the product definition section for the
default embedded Flash mapping. Locked sectors can be unlocked to be erased and then pro-
grammed with another application or other data.
The lock sequence is:
A programming error, where a bad keyword and/or an invalid command have been written in the
MC_FCR register, may be detected in the MC_FSR register after a programming sequence.
It is possible to clear lock bits that were set previously. Then the locked region can be erased or
programmed. The unlock sequence is:
A programming error, where a bad keyword and/or an invalid command have been written in the
MC_FCR register, may be detected in the MC_FSR register after a programming sequence.
The Unlock command programs the lock bit to 1; the corresponding bit LOCKSx in MC_FSR
reads 0. The Lock command programs the lock bit to 0; the corresponding bit LOCKSx in
MC_FSR reads 1.
Note:
• Programming Error: A bad keyword and/or an invalid command have been written in the
• Lock Error: At least one lock region to be erased is protected. The erase command has been
• The Flash Command register must be written with the following value:
• When locking completes, the bit FRDY in the Flash Programming Status Register (MC_FSR)
• The Flash Command register must be written with the following value:
• When the unlock completes, the bit FRDY in the Flash Programming Status Register
MC_FCR register.
refused and no page has been erased. A Clear Lock Bit command must be executed
previously to unlock the corresponding lock regions.
(0x5A << 24) | (lockPageNumber << 8 & PAGEN) | SLB
lockPageNumber is a page of the corresponding lock region.
rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line
of the Memory Controller is activated.
(0x5A << 24) | (lockPageNumber << 8 & PAGEN) | CLB
lockPageNumber is a page of the corresponding lock region.
(MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the
interrupt line of the Memory Controller is activated.
Access to the Flash in Read Mode is permitted when a Lock or Unlock command is performed.
6222F–ATARM–14-Jan-11
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