AT91SAM7SE256-AU Atmel, AT91SAM7SE256-AU Datasheet - Page 48
![IC ARM7 MCU FLASH 256K 128-LQFP](/photos/6/71/67112/128-lqfp_sml.jpg)
AT91SAM7SE256-AU
Manufacturer Part Number
AT91SAM7SE256-AU
Description
IC ARM7 MCU FLASH 256K 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT88SC-SDK1.pdf
(90 pages)
2.AT91SAM7SE256-AU.pdf
(673 pages)
3.AT91SAM7SE32-AU.pdf
(655 pages)
Specifications of AT91SAM7SE256-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
55 MHz
Number Of Programmable I/os
88
Number Of Timers
2
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7SE-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Controller Family/series
AT91SAM7xxxxx
No. Of I/o's
88
Ram Memory Size
32KB
Cpu Speed
48MHz
No. Of Timers
3
Rohs Compliant
Yes
For Use With
AT91SAM7SE-EK - EVAL BOARD FOR AT91SAM7SEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7SE256-AU
Manufacturer:
ATMEL
Quantity:
165
- Current page: 48 of 673
- Download datasheet (11Mb)
48
SAM7SE512/256/32 Preliminary
access to the Program Counter (ARM Register 15), the Link Register (ARM Register 14) and the
Stack Pointer (ARM Register 13). Further instructions allow limited access to the ARM registers
8 to 15.
Table 11-3
Table 11-3.
Mnemonic
MOV
ADD
SUB
CMP
TST
AND
EOR
LSL
ASR
MUL
B
BX
LDR
LDRH
LDRB
LDRSH
LDMIA
PUSH
gives the Thumb instruction mnemonic list.
Operation
Move
Add
Subtract
Compare
Test
Logical AND
Logical Exclusive OR
Logical Shift Left
Arithmetic Shift Right
Multiply
Branch and Exchange
Load Word
Load Half Word
Load Byte
Load Signed Halfword
Load Multiple
Push Register to stack
Thumb Instruction Mnemonic List
Branch
SWI
Mnemonic
MVN
ADC
SBC
CMN
NEG
BIC
ORR
LSR
ROR
BL
STR
STRH
STRB
LDRSB
STMIA
POP
Operation
Move Not
Add with Carry
Subtract with Carry
Compare Negated
Negate
Bit Clear
Logical (inclusive) OR
Logical Shift Right
Rotate Right
Branch and Link
Software Interrupt
Store Word
Store Half Word
Store Byte
Load Signed Byte
Store Multiple
Pop Register from stack
6222F–ATARM–14-Jan-11
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