AT91SAM7SE256-AU Atmel, AT91SAM7SE256-AU Datasheet - Page 661

• Manufacturer Part Number: AT91SAM7SE256-AU
• Description: IC ARM7 MCU FLASH 256K 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7SE256-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: EBI/EMI, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 88
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 2
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7SE-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AT91SAM7xxxxx
• No. Of I/o's: 88
• Ram Memory Size: 32KB
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• For Use With: AT91SAM7SE-EK - EVAL BOARD FOR AT91SAM7SEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6222F–ATARM–14-Jan-11
Version
6222C
Version
6222B
Comments
Overview,
“not 5V tolerant”.
INL and DNL updated in
“Features”
Section 7.1 ”ARM7TDMI
Section 7.8 ”Peripheral DMA Controller”
Section 7.5 ”Static Memory Controller”
operations
Clock Generator, Removed information on capacitor load value in
Connections” Figure 28-2 ”Typical Crystal Connection” on page
DBGU, Debug Unit Chip ID Register,
internal RAM size and
added descriptions for CAP7, AT91SAM7AQxx series and CAP11
EBI,
NAND Flash column, added notes to table for SDRAM, NAND FLash and references to app notes.
Figure 21-1 ”Organization of the External Bus Interface”
Section 21.7.6.1 ”Hardware Configuration”
Section 21.7.7.1 ”Hardware Configuration”
Comments
Section 40. ”SAM7SE512/256/32 Electrical Characteristics”
Table 40-12, “XIN Clock Electrical Characteristics”
Table 40-2, “DC
VDDIO DC supplies 3.3V and 1.8V defined
Table 40-7, “Power Consumption for Different
assigned to Ultra Low Power mode.
Table 40-5, “DC Flash Characteristics
Section 41. ”SAM7SE512/256/32 Mechanical Characteristics”
LQFP-package, JESD97 Classification is e3.
Thermal Considerations removed.
Section 43. ”SAM7SE512/256/32 Errata”
Section 43.2.1 ”Analog-to-Digital Converter
Section 43.2.5 ”SDRAM Controller
Section 43.2.6.1 ”SPI: Baudrate Set to
Section 43.2.6.2 ”SPI: Bad Serial Clock Generation on 2nd Chip
Section 43.2.7.4 ”SSC: Last RK Clock Cycle when RK Outputs a Clock During Data
Section 43.2.7.5 ”SSC: First RK Clock Cycle when Rk Outputs a Clock During Data
Section 43.2.9.3 ”USART: DCD is Active High Instead of
Section 43.2.9.4 ”USART: RXBRK Flag Error in Asynchronous
Table 21-3, “EBI Pins and External Static Device Connections,” on page
Section 6.1 ”JTAG Port
on page 2, Fully Static Operation: added up to 55 MHz at 1.8V and 85°C worst case conditions
Characteristics”, junction temperature removed and
Section 7.6 ”SDRAM Controller”
“ARCH: Architecture Identifier” on page 321
Section 10.14 “Analog-to-Digital Converter” on page 42
Processor”, Runs at up to 55 MHz, providing 0.9 MIPS/MHz (core supplied with 1.8V)
Pins”,
(SDRAMC)”, added to errata.
“SRAMSIZ: Internal SRAM Size” on page 320
SAM7SE32”, Max standby current updated.
Multiple device adaptability: compliant w/PSRAM in synchronous
1”, Problem Fix/Workaround = None.
PDC priority list added.
Section 6.3 ”Reset
A25 removed from CFRNW in CompactFlash
A25 removed from CFRNW in CompactFlash True IDE
(ADC)”, added to errata.
Modes”: Footnote assigned to Flash In standby mode. Footnote
Mobile SDRAM controller added to SDRAMC description
VXIN_IL, VXIN_IH updated
SDCK is not multiplexed with PIO
SAM7SE512/256/32 Preliminary
Low”, added to errata.
Pin”,
Mode”, added to errata.
272, updated, CL1 and CL2 labels removed.
Select”, added to errata.
Section 6.5 ”SDCK
updated bin values for 0x60 and 0xF0, and
Section 28.3.1 ”Main Oscillator
138, I/O[8:15] bits added in
updated w/AT91SAM7L
Transfer”, added to errata.
Transfer”, added to errata.
Pin”, removed statement:
Change
Request
Ref.
3826
4005
3924
3833
review
3282
3861
3828
3369
3807
3742/3743
/
3852
3924
4044/3836
Change
Request
Ref.
5007
rfo
4657
4598
rfo
4971/5007
4657
5007/4751
/4642
661