AT91SAM7SE256-AU Atmel, AT91SAM7SE256-AU Datasheet - Page 167

IC ARM7 MCU FLASH 256K 128-LQFP

AT91SAM7SE256-AU

Manufacturer Part Number
AT91SAM7SE256-AU
Description
IC ARM7 MCU FLASH 256K 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets

Specifications of AT91SAM7SE256-AU

Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
55 MHz
Number Of Programmable I/os
88
Number Of Timers
2
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7SE-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Controller Family/series
AT91SAM7xxxxx
No. Of I/o's
88
Ram Memory Size
32KB
Cpu Speed
48MHz
No. Of Timers
3
Rohs Compliant
Yes
For Use With
AT91SAM7SE-EK - EVAL BOARD FOR AT91SAM7SEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM7SE256-AU
Manufacturer:
ATMEL
Quantity:
165
Part Number:
AT91SAM7SE256-AU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT91SAM7SE256-AU-999
Manufacturer:
Atmel
Quantity:
10 000
22.6.2.4
6222F–ATARM–14-Jan-11
Write Data Hold Time
Figure 22-8
on NCS2 (BAT = 1).
Figure 22-8. Connection to a 16-bit Data Path Device without Byte Write Capability
During write cycles, data output becomes valid after the rising edge of MCK and remains valid
after the rising edge of NWE. During a write access, the data remain on the bus 1/2 period of
MCK after the rising edge of NWE. See
Figure 22-9. Write Access with 0 Wait State
D[15:0]
A[22:0]
NWE
MCK
NCS
shows how to connect a 16-bit device without byte access (e.g., Flash device type)
SMC
D[15:8]
A[19:1]
D[7:0]
NCS2
NWE
NRD
NUB
NLB
SAM7SE512/256/32 Preliminary
Figure 22-9
and
Figure
D[7:0]
D[15:8]
A[18:0]
Write Enable
Output Enable
Memory Enable
22-10.
167

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