AT91SAM7SE256-AU Atmel, AT91SAM7SE256-AU Datasheet - Page 662

• Manufacturer Part Number: AT91SAM7SE256-AU
• Description: IC ARM7 MCU FLASH 256K 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7SE256-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: EBI/EMI, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 88
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 2
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7SE-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AT91SAM7xxxxx
• No. Of I/o's: 88
• Ram Memory Size: 32KB
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• For Use With: AT91SAM7SE-EK - EVAL BOARD FOR AT91SAM7SEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

662
Version
6222B
SAM7SE512/256/32 Preliminary
Comments
Electrical Characteristics,
Section 40.4.3 ”Crystal Characteristics”
Table 40-12, “XIN Clock Electrical Characteristics”
Section 40.7 ”ADC Characteristics”
“Transfer
INL and DNL updated in
Section 40.8.4 ”SMC
page 634
Figure 40-8 ”SMC Signals in Memory Interface Mode”
SMC timings updated to be concordant with signals listed in
Section 40.8.6 ”Embedded Flash Characteristics”
States (VDDCORE = 1.65V)”
Table 40-20, “Master Clock Waveform
Table 40-10, “Main Oscillator Characteristics”
Table 40-7, “Power Consumption for Different Modes”
Table 40-32, “Embedded Flash Wait States (VDDCORE = 1.65V)”
ECCC,
Access” on page 220
Register” on page 228
ERRATA,
end of the starting bit, a character can be lost”...........
MC,
PIO,
User Interface,
PIO_ODSR, PIO_PDSR table cells.
SDRAMC,
Figure 23-1 on page
SMC,
32-bit bus removed from bit field description
“SMC Chip Select Registers” on page
appear in the bit field description:
Wait States” column added to this table and NRD Pulse Length is defined in Standard Read and Early Read
Protocols.
Note 1 assigned to table describing bit fields
Read and Write Signal Hold Time” on page
GLOBAL All references to A25 address line changed to be A22 (23-bit address bus)
Note specific to ECC Controller added to
“Overview” on page
“External Memory Mapping” on page
Figure 22-3 on page
Figure 22-32 on page
Figure
Section 18.4.5 ”Memory Protection
Section 34.4.5 ”Synchronous Data
Figure
22-45,
Section 24.3 ”Functional Description”
Characteristics”. Reference to Data Converter Terminology added below table.
Section 43.2.9.1 ”USART: CTS in Hardware
and in the following two figures.
Section 23.1 “Overview” on page
22-9,
Figure 22-46
Table 34-2, “PIO Register Mapping,” on page
Figure
161, Address space is 64 Mbytes and the address bus is 23 bits.
199, SDCK signal in the Block Diagram updated.
164, maximum address space per device is 8 Mbytes.
Signals”,A25 Address line changed to A22.
updated.
183,change in values on [D15:0] line.
instruction updated.
Section 10.14 “Analog-to-Digital Converter” on page 42
22-10,
and
and added
Section 24.4.4 ”ECC Parity Register”
Figure 22-47 on page 198
Figure
“NWS: Number of Wait States” on page
INL and DNL updated and Absolute accuracy added to
163, external address bus is 23 bits.
196, section restructured with table moved from the end of the section to
Parameters”, updated w/V
TCHXIN and TCHLXIN updated, TCLCH and TCHCL added to
Output”, PIO_OWSR typo corrected.
Unit”, initialization guidelines updated at end of section.
22-11,
Table 40-33, “Embedded Flash Wait States (VDDCORE = 1.8V)”
“RWHOLD: Read and Write Signal Hold
197.
“BAT: Byte Access Type” on page 196
199, Mobile SDRAM controller added to SDRAMC description
“RWSETUP: Read and Write Signal Setup
and
added schematic in footnote to C
Figure
updated. Note added t
Section 24.3.1 ”Write Access”
and
and
22-12,
DDM and DDP pins must be left floating.
Handshaking”, updated.....”if CTS goes high near the
Figure 40-2 ”XIN Clock Timing”
replaced.
Figure 40-9 ”SM Signals in LCD Interface Mode”
Table 40-25
446, footnotes updated on PIO_PSR,
Figure 22-13
Table 40-25 on page 632
DDCORE
footnote
and
oTable 40-32, “Embedded Flash Wait
= 1.8V, Max = 55 MHz
thru
Section 24.4.5 “ECC NParity
196. “Don’t Care” and “Number of
and
(2)
Table
added.
L
Figure 22-25
and
and C
Time”bit field description.
40-28.
Section 24.3.2 “Read
LEXT
has been added.
Time”and
thru
Table 40-19,
symbols
replaced
Table 40-28 on
“RWHOLD:
6222F–ATARM–14-Jan-11
Change
Request
Ref.
3966
4005
4044/3836
3924
3868
3829
review
3970
3955
4045
3289
3974
3826
review
3846
3847
3848/4182
3863/3864
3886
review