AT91SAM7SE256-AU Atmel, AT91SAM7SE256-AU Datasheet - Page 208

• Manufacturer Part Number: AT91SAM7SE256-AU
• Description: IC ARM7 MCU FLASH 256K 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7SE256-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: EBI/EMI, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 88
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 2
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7SE-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AT91SAM7xxxxx
• No. Of I/o's: 88
• Ram Memory Size: 32KB
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• For Use With: AT91SAM7SE-EK - EVAL BOARD FOR AT91SAM7SEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

23.6.5
23.6.5.1
Figure 23-7. Self-refresh Mode Behavior
208
SDRAMC_SRR
SDCKE
A[12:0]
SDWE
SDCK
SDCS
Write
RAS
CAS
SAM7SE512/256/32 Preliminary
Power Management
Self-refresh Mode
SRCB = 1
Self-refresh mode is used in power-down mode, i.e., when no access to the SDRAM device is
possible. In this case, power consumption is very low. The mode is activated by programming
the self-refresh command bit (SRCB) in SDRAMC_SRR. In self-refresh mode, the SDRAM
device retains data without external clocking and provides its own internal clocking, thus per-
forming its own auto-refresh cycles. All the inputs to the SDRAM device become “don’t care”
except SDCKE, which remains low. As soon as the SDRAM device is selected, the SDRAM
Controller provides a sequence of commands and exits self-refresh mode, so the self-refresh
command bit is disabled.
To re-activate this mode, the self-refresh command bit must be re-programmed.
The SDRAM device must remain in self-refresh mode for a minimum period of t
remain in self-refresh mode for an indefinite period. This is described in
Self Refresh Mode
to the SDRAM Controller
Access Request
T
Figure 23-7
XSR
= 3
6222F–ATARM–14-Jan-11
RAS
below.
Row
and may