AT91SAM7SE256-AU Atmel, AT91SAM7SE256-AU Datasheet - Page 161

• Manufacturer Part Number: AT91SAM7SE256-AU
• Description: IC ARM7 MCU FLASH 256K 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7SE256-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: EBI/EMI, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 88
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 2
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7SE-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AT91SAM7xxxxx
• No. Of I/o's: 88
• Ram Memory Size: 32KB
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• For Use With: AT91SAM7SE-EK - EVAL BOARD FOR AT91SAM7SEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22. Static Memory Controller (SMC)
22.1
22.2
6222F–ATARM–14-Jan-11
Overview
Block Diagram
The Static Memory Controller (SMC) generates the signals that control the access to external
static memory or peripheral devices. The SMC is fully programmable. It has eight chip selects
and a 23-bit address bus. The 16-bit data bus can be configured to interface with 8- or 16-bit
external devices. Separate read and write control signals allow for direct memory and peripheral
interfacing. The SMC supports different access protocols allowing single clock cycle memory
accesses. It also provides an external wait request capability.
Figure 22-1. Static Memory Controller Block Diagram
Controller
Memory
PMC
Chip Select
SMC
MCK
SMC
SAM7SE512/256/32 Preliminary
APB
User Interface
Controller
PIO
NCS[7:0]
NRD
NWR0/NWE
NWR1/NUB
A0/NLB
A[22:1]
D[15:0]
NWAIT
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