MCHC11F1CFNE3 Freescale Semiconductor, MCHC11F1CFNE3 Datasheet - Page 100

IC MCU 8BIT 1K RAM 68-PLCC

MCHC11F1CFNE3

Manufacturer Part Number
MCHC11F1CFNE3
Description
IC MCU 8BIT 1K RAM 68-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MCHC11F1CFNE3

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
30
Program Memory Type
ROMless
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.75 V ~ 5.25 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
68-PLCC
A/d Inputs
8-Channel, 8-Bit
Eeprom Memory
512 Bytes
Input Output
30
Interface
SCI/SPI
Memory Type
EPROM
Number Of Bits
8
Package Type
68-pin PLCC
Programmable Memory
0 Bytes
Timers
3-16-bit
Voltage, Range
3-5.5 V
Controller Family/series
68HC11
No. Of I/o's
30
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
3MHz
No. Of Timers
1
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Processor Series
HC11F
Core
HC11
Data Bus Width
8 bit
Program Memory Size
512 B
Data Ram Size
1 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
3 MHz
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Size
-
Lead Free Status / Rohs Status
RoHS Compliant part

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8.2 SPI Transfer Formats
8-2
During an SPI transfer, data is simultaneously transmitted and received. A serial clock
line synchronizes shifting and sampling of the information on the two serial data lines.
A slave select line allows individual selection of a slave SPI device; slave devices that
are not selected do not interfere with SPI bus activities. On a master SPI device, the
select line can optionally be used to indicate a multiple master bus contention. Refer
to Figure 8-2.
SPSR SPI STATUS REGISTER
2
MCU CLOCK
INTERNAL
DIVIDER
SELECT
4
SPI CONTROL
16
32
SPI INTERRUPT
SPI CLOCK (MASTER)
REQUEST
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 8-1 SPI Block Diagram
SERIAL PERIPHERAL INTERFACE
8
Go to: www.freescale.com
MSTR
SPE
SPIE
DATA BUS
INTERNAL
MSB
8
8-BIT SHIFT REGISTER
READ DATA BUFFER
SPCR SPI CONTROL REGISTER
8
CLOCK
LOGIC
LSB
CLOCK
S
S
S
M
M
M
CONTROL
LOGIC
PIN
TECHNICAL DATA
MC68HC11F1
MISO/
MOSI/
SCK/
PD2
PD3
PD4
PD5
SS/

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