MCHC11F1CFNE3 Freescale Semiconductor, MCHC11F1CFNE3 Datasheet - Page 111

• Manufacturer Part Number: MCHC11F1CFNE3
• Description: IC MCU 8BIT 1K RAM 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MCHC11F1CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 30
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• A/d Inputs: 8-Channel, 8-Bit
• Eeprom Memory: 512 Bytes
• Input Output: 30
• Interface: SCI/SPI
• Memory Type: EPROM
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 0 Bytes
• Timers: 3-16-bit
• Voltage, Range: 3-5.5 V
• Controller Family/series: 68HC11
• No. Of I/o's: 30
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC11F
• Core: HC11
• Data Bus Width: 8 bit
• Program Memory Size: 512 B
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: RoHS Compliant part

9.2 Input Capture
9.2.1 Timer Control Register 2
TCTL2 — Timer Control 2
EDGxB and EDGxA — Input Capture Edge Control
TECHNICAL DATA
RESET:
The input capture function records the time an external event occurs by latching the
value of the free-running counter when a selected edge is detected at the associated
timer input pin. Software can store latched values and use them to compute the peri-
odicity and duration of events. For example, by storing the times of successive edges
of an incoming signal, software can determine the period and pulse width of a signal.
To measure period, two successive edges of the same polarity are captured. To mea-
sure pulse width, two alternate polarity edges are captured.
In most cases, input capture edges are asynchronous to the internal timer counter,
which is clocked relative to an internal clock (PH2). These asynchronous capture re-
quests are synchronized to PH2 so that the latching occurs on the opposite half cycle
of PH2 from when the timer counter is being incremented. This synchronization pro-
cess introduces a delay from when the edge occurs to when the counter value is de-
tected. Because these delays offset each other when the time between two edges is
being measured, the delay can be ignored. When an input capture is being used with
an output compare, there is a similar delay between the actual compare point and
when the output pin changes state.
The control and status bits that implement the input capture functions are contained in
the PACTL, TCTL2, TMSK1, and TFLG1 registers.
To configure port A bit 3 as an input capture, clear the DDA3 bit of the DDRA register.
Note that this bit is cleared out of reset. To enable PA3 as the fourth input capture, set
the I4/O5 bit in the PACTL register. Otherwise, PA3 is configured as a fifth output com-
pare out of reset, with bit I4/O5 being cleared. If the DDA3 bit is set (configuring PA3
as an output), and IC4 is enabled, then writes to PA3 cause edges on the pin to result
in input captures. Writing to TI4/O5 has no effect when the TI4/O5 register is acting as
IC4.
Use the control bits of this register to program input capture functions to detect a par-
ticular edge polarity on the corresponding timer input pin. Each of the input capture
functions can be independently configured to detect rising edges only, falling edges
only, any edge (rising or falling), or to disable the input capture function. The input cap-
ture functions operate independently of each other and can capture the same TCNT
value if the input edges are detected within the same timer count cycle.
There are four pairs of these bits. Each pair is cleared to zero by reset and must be
encoded to configure the corresponding input capture edge detector circuit. IC4 func-
tions only if the I4/O5 bit in the PACTL register is set. Refer to Table 9-2 for timer con-
trol configuration.
EDG4B
Bit 7
0
EDG4A
6
0
Freescale Semiconductor, Inc.
For More Information On This Product,
EDG1B
5
0
Go to: www.freescale.com
TIMING SYSTEM
EDG1A
4
0
EDG2B
0
3
EDG2A
2
0
EDG3B
1
0
EDG3A
Bit 0
0
$1021
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