MCHC11F1CFNE3 Freescale Semiconductor, MCHC11F1CFNE3 Datasheet - Page 32

• Manufacturer Part Number: MCHC11F1CFNE3
• Description: IC MCU 8BIT 1K RAM 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MCHC11F1CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 30
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• A/d Inputs: 8-Channel, 8-Bit
• Eeprom Memory: 512 Bytes
• Input Output: 30
• Interface: SCI/SPI
• Memory Type: EPROM
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 0 Bytes
• Timers: 3-16-bit
• Voltage, Range: 3-5.5 V
• Controller Family/series: 68HC11
• No. Of I/o's: 30
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC11F
• Core: HC11
• Data Bus Width: 8 bit
• Program Memory Size: 512 B
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: RoHS Compliant part

3.4.2 Direct
3.4.3 Extended
3.4.4 Indexed
3.4.5 Inherent
3.4.6 Relative
3.5 Instruction Set
3-8
(if prebyte is required) byte immediate instructions. The effective address is the ad-
dress of the byte following the instruction.
In the direct addressing mode, the low-order byte of the operand address is contained
in a single byte following the opcode, and the high-order byte of the address is as-
sumed to be $00. Addresses $00–$FF are thus accessed directly, using two-byte in-
structions. Execution time is reduced by eliminating the additional memory access
required for the high-order address byte. In most applications, this 256-byte area is re-
served for frequently referenced data. In M68HC11 MCUs, the memory map can be
configured for combinations of internal registers, RAM, or external memory to occupy
these addresses.
In the extended addressing mode, the effective address of the argument is contained
in two bytes following the opcode byte. These are three-byte instructions (or four-byte
instructions if a prebyte is required). One or two bytes are needed for the opcode and
two for the effective address.
In the indexed addressing mode, an 8-bit unsigned offset contained in the instruction
is added to the value contained in an index register (IX or IY). The sum is the effective
address. This addressing mode allows referencing any memory location in the 64
Kbyte address space. These are two- to five-byte instructions, depending on whether
or not a prebyte is required.
In the inherent addressing mode, all the information necessary to execute the instruc-
tion is contained in the opcode. Operations that use only the index registers or accu-
mulators, as well as control instructions with no arguments, are included in this
addressing mode. These are one- or two-byte instructions.
The relative addressing mode is used only for branch instructions. If the branch con-
dition is true, an 8-bit signed offset included in the instruction is added to the contents
of the program counter to form the effective branch address. Otherwise, control pro-
ceeds to the next instruction. These are usually two-byte instructions.
Refer to Table 3-2, which shows all the M68HC11 instructions in all possible address-
ing modes. For each instruction, the table shows the operand construction, the num-
ber of machine code bytes, and execution time in CPU E clock cycles.
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TECHNICAL DATA
MC68HC11F1