MCHC11F1CFNE3 Freescale Semiconductor, MCHC11F1CFNE3 Datasheet - Page 114

• Manufacturer Part Number: MCHC11F1CFNE3
• Description: IC MCU 8BIT 1K RAM 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MCHC11F1CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 30
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• A/d Inputs: 8-Channel, 8-Bit
• Eeprom Memory: 512 Bytes
• Input Output: 30
• Interface: SCI/SPI
• Memory Type: EPROM
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 0 Bytes
• Timers: 3-16-bit
• Voltage, Range: 3-5.5 V
• Controller Family/series: 68HC11
• No. Of I/o's: 30
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC11F
• Core: HC11
• Data Bus Width: 8 bit
• Program Memory Size: 512 B
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: RoHS Compliant part

TOC1–TOC4 — Timer Output Compare
9.3.2 Timer Compare Force Register
CFORC — Timer Compare Force
FOC[1:5] — Force Output Comparison
Bits [2:0] — Not implemented
9.3.3 Output Compare Mask Registers
9-8
$101C
$101D
$101A
$101B
$1016
$1017
$1018
$1019
RESET:
All TOCx register pairs reset to ones ($FFFF).
The CFORC register allows forced early compares. FOC[1:5] correspond to the five
output compares. These bits are set for each output compare that is to be forced. The
action taken as a result of a forced compare is the same as if there were a match be-
tween the OCx register and the free-running counter, except that the corresponding
interrupt status flag bits are not set. The forced channels trigger their programmed pin
actions to occur at the next timer count transition after the write to CFORC.
The CFORC bits should not be used on an output compare function that is pro-
grammed to toggle its output on a successful compare because a normal compare that
occurs immediately before or after the force can result in an undesirable operation.
When the FOC bit associated with an output compare circuit is set, the output compare
circuit immediately performs the action it is programmed to do when an output match
occurs.
Always read zero
Use OC1M with OC1 to specify the bits of port A that are affected by a successful OC1
compare. The bits of the OC1M register correspond to PA[7:3].
0 = Not affected
1 = Output x action occurs
Bit 15
Bit 15
Bit 15
Bit 15
Bit 7
Bit 7
Bit 7
Bit 7
FOC1
Bit 7
0
14
14
14
14
6
6
6
6
FOC2
6
0
Freescale Semiconductor, Inc.
For More Information On This Product,
13
13
13
13
5
5
5
5
FOC3
5
0
Go to: www.freescale.com
12
12
12
12
4
4
4
4
TIMING SYSTEM
FOC4
4
0
11
11
11
11
3
3
3
3
FOC5
0
3
10
10
10
10
2
2
2
2
—
2
0
9
1
9
1
9
1
9
1
—
1
0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
TECHNICAL DATA
Bit 0
$1016–$101D
—
0
MC68HC11F1
TOC1 (High)
TOC1 (Low)
TOC2 (High)
TOC2 (Low)
TOC3 (High)
TOC3 (Low)
TOC4 (High)
TOC4 (Low)
$100B