MCHC11F1CFNE3 Freescale Semiconductor, MCHC11F1CFNE3 Datasheet - Page 65

• Manufacturer Part Number: MCHC11F1CFNE3
• Description: IC MCU 8BIT 1K RAM 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MCHC11F1CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 30
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• A/d Inputs: 8-Channel, 8-Bit
• Eeprom Memory: 512 Bytes
• Input Output: 30
• Interface: SCI/SPI
• Memory Type: EPROM
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 0 Bytes
• Timers: 3-16-bit
• Voltage, Range: 3-5.5 V
• Controller Family/series: 68HC11
• No. Of I/o's: 30
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC11F
• Core: HC11
• Data Bus Width: 8 bit
• Program Memory Size: 512 B
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: RoHS Compliant part

5.1.5 OPTION Register
OPTION — System Configuration Options
ADPU — Analog-to-Digital Converter Power-Up
CSEL — Clock Select
IRQE — Configure IRQ for Edge-Sensitive Only Operation
DLY — Enable Oscillator Start-up Delay
CME — Clock Monitor Enable
FCME — Force Clock Monitor Enable
TECHNICAL DATA
RESET:
Semiconductor wafer processing causes variations of the RC time-out values between
individual devices. An E-clock frequency below 10 kHz is detected as a clock monitor
error. An E-clock frequency of 200 kHz or more prevents clock monitor errors. Using
the clock monitor function when the E-clock is below 200 kHz is not recommended.
Special considerations are needed when a STOP instruction is executed and the clock
monitor is enabled. Because the STOP function causes the clocks to be halted, the
clock monitor function generates a reset sequence if it is enabled at the time the STOP
mode was initiated. Before executing a STOP instruction, clear to zero the CME bit in
the OPTION register to disable the clock monitor. After recovery from STOP, set the
CME bit to logic one to enable the clock monitor.
Refer to SECTION 10 ANALOG-TO-DIGITAL CONVERTER.
Refer to SECTION 10 ANALOG-TO-DIGITAL CONVERTER.
This control bit can be read or written at any time and controls whether or not the in-
ternal clock monitor circuit triggers a reset sequence when the system clock is slow or
absent. When it is clear, the clock monitor circuit is disabled, and when it is set, the
clock monitor circuit is enabled. Reset clears the CME bit.
To use STOP mode, the FCME bit must equal zero.
*Can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes.
0 = Low level sensitive operation.
1 = Falling edge sensitive only operation.
0 = The oscillator start-up delay coming out of STOP is bypassed and the MCU re-
1 = A delay of approximately 4000 E-clock cycles is imposed as the MCU is started
0 = Clock monitor follows the state of the CME bit.
1 = Clock monitor circuit is enabled until next reset
sumes processing within about four bus cycles.
up from the STOP power-saving mode.
ADPU
Bit 7
0
CSEL
6
0
Freescale Semiconductor, Inc.
For More Information On This Product,
IRQE*
5
0
RESETS AND INTERRUPTS
Go to: www.freescale.com
DLY*
4
1
CME
0
3
FCME*
2
0
CR1*
1
0
CR0*
Bit 0
0
$1039
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