TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 17

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

13. Synchronous Serial Port (SSP)
12.7 Clock Control......................................................................................................................383
12.8 Transmit / Receive Buffer and FIFO..................................................................................393
12.9 Status Flag...........................................................................................................................394
12.10 Error Flag...........................................................................................................................394
12.11 Receive..............................................................................................................................396
12.12 Transmission......................................................................................................................401
12.13 Handshake Function..........................................................................................................405
12.14 Interrupt / Error Generation Timing.................................................................................406
12.15 Software Reset...................................................................................................................408
12.16 Operation in Each Mode...................................................................................................409
13.1 Overview..............................................................................................................................423
13.2 Block Diagram.....................................................................................................................424
13.3 Register................................................................................................................................425
12.7.1
12.7.2
12.8.1
12.8.2
12.8.3
12.10.1
12.10.2
12.10.3
12.11.1
12.11.2
12.11.3
12.12.1
12.12.2
12.12.3
12.14.1
12.14.2
12.14.3
12.16.1
12.16.2
12.16.3
12.16.4
12.7.2.1
12.7.2.2
12.11.2.1
12.11.2.2
12.11.3.1
12.11.3.2
12.11.3.3
12.11.3.4
12.11.3.5
12.11.3.6
12.12.2.1
12.12.2.2
12.12.3.1
12.12.3.2
12.12.3.3
12.12.3.4
12.14.1.1
12.14.1.2
12.14.2.1
12.14.2.2
12.14.3.1
12.14.3.2
12.16.1.1
12.16.1.2
12.16.1.3
12.16.4.1
12.16.4.2
Prescaler.........................................................................................................................................................................383
Serial Clock Generation Circuit....................................................................................................................................389
Configuration.................................................................................................................................................................393
Transmit / Receive Buffer.............................................................................................................................................393
FIFO...............................................................................................................................................................................393
Mode 3 (9-bit UART Mode).......................................................................................................................................421
OERR Flag..................................................................................................................................................................394
PERR Flag...................................................................................................................................................................395
FERR Flag...................................................................................................................................................................395
Receive Counter..........................................................................................................................................................396
Receive Control Unit...................................................................................................................................................396
Receive Operation.......................................................................................................................................................396
Transmission Counter..................................................................................................................................................401
Transmission Control..................................................................................................................................................401
Transmit Operation......................................................................................................................................................402
RX Interrupt.................................................................................................................................................................406
TX interrupt.................................................................................................................................................................407
Error Generation..........................................................................................................................................................408
Mode 0 (I/O Interface Mode)......................................................................................................................................409
Mode 1 (7-bit UART Mode).......................................................................................................................................420
Mode 2 (8-bit UART Mode).......................................................................................................................................420
Baud Rate Generator
Clock Selection Circuit
I/O interface mode
UART Mode
Receive Buffer
Receive FIFO Operation
I/O interface mode with SCLK output
Read Received Data
Wake-up Function
Overrun Error
I/O interface Mode
UART Mode
Operation of Transmission Buffer
Transmit FIFO Operation
I/O interface Mode/Transmission by SCLK Output
Underrun Error
Single Buffer / Double Buffer
FIFO
Single Buffer / Double Buffer
FIFO
UART Mode
I/O Interface Mode
Transmitting Data
Receive
Transmit and Receive (Full duplex)
Wake-up Function
Protocol
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