TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 509

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

<SIOS>
<SIOF>
<SEF>
SCKx pin (output)
SOx pin
SIx pin
INTSBIx
interrupt request
SBIxDBR
14.8.2.3
ting SBIxCR1<SIOS> to "1" enables transmission and reception.The transmit data is output through the
SOx pin at the falling of the serial clock, and the received data is taken in through the SI pin at the rising
of the serial clock, with the least-significant bit (LSB) first. Once the shift register is loaded with the 8-
bit data, it transfers the received data to SBIxDBR and the INTSBIx interrupt request is generated.The in-
terrupt service program reads the received data from the data buffer register and writes the next transmit da-
ta. Because SBIxDBR is shared between transmit and receive operations, the received data must be read be-
fore the next transmit data is written.
data is read and the next transmit data is written.
clock. Therefore, the received data must be read and the next transmit data must be written before the
next shift operation is started.The maximum data transfer rate for the external clock operation varies depend-
ing on the maximum latency between when the interrupt request is generated and when the transmit data
is written.
put in a period from setting <SIOF> to "1" to the falling edge of SCK.
SBIxCR1<SIOINH> to "1" in the INTSBIx interrupt service program. If <SIOS> is cleared, transmission
and reception continue until the received data is fully transferred to SBIxDBR. The program checks
SBIxSR<SIOF> to determine whether transmission and reception have come to an end. <SIOF> is
cleared to "0" at the end of transmission and reception.If <SIOINH> is set to "1", the transmission and re-
ception is aborted immediately and <SIOF> is cleared to "0".
Set the control register to the transfer/receive mode. Then writing the transmit data to SBIxDBR and set-
In the internal clock operation, the serial clock will be automatically in the wait state until the received
In the external clock mode, shift operations are executed in synchronization with the external serial
At the beginning of transmission, the same value as in the last bit of the previously transmitted data is out-
Transmission and reception can be terminated by clearing <SIOS> to "0" or setting
Note:The contents of SBIxDBR will not be retained after the transfer mode is changed. The ongo-
Write the transmitted
data(a)
Figure 14-20 Transmit/Receive Mode (Example: Internal Clock)
8-bit transmit/receive mode
ing transmission and reception must be completed by clearing <SIOS> to "0" and the last re-
ceived data must be read before the transfer mode is changed.
*
a
a
c
0
0
a
c
1
1
a
c
2
2
a
c
3
3
a
c
4
4
a
c
5
5
Read the received
data(c)
Page 485
a
c
6
6
a
c
7
7
c
Write the transmitted
data(b)
b
b
d
0
0
b
d
1
1
b
d
2
2
<SIOS> is cleard.
b
d
3
3
b
d
4
4
b
d
5
5
TMPM362F10FG
b
d
6
6
Read the received
data(d)
b
d
7
7
d