TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 422

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

12.11
Receive
12.11.3.2
RX interrupt (INTRXx)
Receive FIFO First stage
SCxMOD2<RBFLL>
Receive shift register
SCxMOD0<RXE>
Receive buffer
buffer full flag is cleared immediately. An interrupt will be generated according to the SCxRFC<RIL> set-
ting.
SCxMOD0<RXE>. When the data is stored all in the receive shift register, receive buffer and receive
FIFO, SCxMOD0<RXE> is automatically cleared and the receive operations finished.
sible to receive a data continuously by reading the data in the FIFO.
SCxMOD1[6:5] =01
SCxFCNF[4:0] = 10111
SCxRFC[1:0] = 00
SCxRFC[7:6] = 01
When FIFO is enabled, the received data is moved from receive buffer to receive FIFO and the receive
The configurations and operations in the half duplex RX mode are described as follows.
After setting of the above FIFO configuration, the data reception is started by writing "1" to the
In the above condition, if the cutaneous reception after reaching the fill level is enabled, it becomes pos-
Note:When the data with parity bit are received in UART mode by using the FIFO, the parity error
Second stage
Third stage
Fourth stage
Receive FIFO Operation
flag is shown the occurring the parity error in the received data.
DATA1
Figure 12-5 Receive FIFO Operation
:Transfer mode is set to half duplex mode
:Automatically inhibits continuous reception after reaching the fill level.
: The number of bytes to be used in the receive FIFO is the same as the interrupt generation fill lev-
el.
:The fill level of FIFO in which generated receive interrupt is set to 4-byte
:Clears receive FIFO and sets the condition of interrupt generation.
DATA2
DATA1
DATA1
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DATA3
DATA2
DATA2
DATA1
DATA4
DATA3
DATA3
DATA2
DATA1
DATA5
DATA4
DATA4
DATA3
DATA2
DATA1
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
TMPM362F10FG
DATA5
DATA4
DATA3
DATA2
DATA1