TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 660

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

22.2
Operation Mode
22.2.3
22.2.3.1
TMPM362F10FG on-chip boot ROM. This boot ROM is a masked ROM. When Single Boot mode is selec-
ted upon reset, the boot ROM is mapped to the address region including the interrupt vector table while the
flash memory is mapped to an address region different from it.
TMPM362F10FG is connected to an external host controller. Via this serial link, a programming routine is
downloaded from the host controller to the TMPM362F10FG on-chip RAM. Then, the flash memory is re-pro-
grammed by executing the programming routine. The host sends out both commands and programming data
to re-program the flash memory. Communications between the SIO4 and the host must follow the protocol de-
scribed later. To secure the contents of the flash memory, the validity of the application’s password is veri-
fied before a programming routine is downloaded into the on-chip RAM. If password matching fails, the trans-
fer of a programming routine itself is aborted. As in the case of User Boot mode, all interrupts including the
non-maskable interrupt (NMI) must be disabled in Single Boot mode while the flash memory is being erased
or programmed. In Single Boot mode, the boot-ROM programs 33are executed in Normal mode.
blocks from accidental corruption during subsequent Single-Chip (Normal mode) operations.
In Single Boot mode, the flash memory can be re-programmed by using a program contained in the
Single Boot mode allows for serial programming of the flash memory. Channel 4 of the SIO (SIO4) of the
Once re-programming is complete, it is recommended to set the write/erase protection to the relevant flash
Single Boot Mode
(1)
(2-A) Using the Program in the On-Chip Boot ROM
executing the programming routine. Since a programming routine and programming data are transfer-
red via the SIO (SIO4), the SIO4 must be connected to a host controller. Prepare a programming rou-
tine (a) on the host controller.
The flash block containing the old version of the program code does not need to be erased before
Step-1
(
TMPM362F10FG
Boot ROM
(or erased state)
Old Application
Program Code
Flash memory
)
Page 636
(I/O)
SIO4
RAM
(Host)
(a)Programming Routine
New Application
Program Code
TMPM362F10FG