TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 705

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

23.3.1
31-26
25-16
15-1
0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
−
BLPRO9 to
BLPRO0
−
RDY/BSY
Note 1: This command must be issued in the ready state. Issuing the command in the busy state may disable
Note 2: The value varies depending on protection applied.
Bit Symbol
FCFLCS (Flash control register)
BLPRO7
(Note2)
31
23
15
0
0
7
0
-
-
-
both correct command transmission and further command input. To exit from the condition, execute sys-
tem reset. System reset requires at least 0.5 ms regardless of the system clock frequency. In this condi-
tion, it takes approx. 2 ms to enable reading after reset.
R
R
R
R
Type
BLPRO6
(Note2)
30
22
14
0
0
6
0
Read as 0.
Protection for Block9 to 0
0: disabled
1: enabled
Protection status bits
Each of the protection bits represents the protection status of the corresponding block. When a bit is set to
"1," it indicates that the block corresponding to the bit is protected. When the block is protected, data can-
not be written to it.
Read as 0.
Ready/Busy (Note 1)
0: Auto operating
1:Auto operation terminated
Ready/Busy flag bit
The RDY/BSY output is provided as a means to monitor the status of automatic operation. This bit is a func-
tion bit for the CPU to monitor the function. When the flash memory is in automatic operation, it outputs
"0" to indicate that it is busy. When the automatic operation is terminated, it returns to the ready state and out-
puts "1" to accept the next command. If the automatic operation has failed, this bit maintains the "0" out-
put. By applying a hardware reset, it returns to "1."
-
-
-
BLPRO5
(Note2)
29
21
13
0
0
5
0
-
-
-
Page 681
BLPRO4
(Note2)
28
20
12
0
0
4
0
-
-
-
BLPRO3
(Note2)
27
19
11
Function
0
0
3
0
-
-
-
BLPRO2
(Note2)
26
18
10
0
0
2
0
-
-
-
BLPRO9
BLPRO1
(Note2)
(Note2)
25
17
9
0
1
0
-
-
TMPM362F10FG
RDY/BSY
BLPRO8
BLPRO0
(Note2)
(Note2)
24
16
8
0
0
1
-