TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 467

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

notifies of the start of transmission. This enables the slave data in the SPDI input line of the master.
ter data and slave data are now set. When another half of SPCLK has passed, the SPCLK master clock pin be-
comes "High". After that, the data is captured at the rising edge of the SPCLK signal and transmitted at its fall-
ing edge.
word have been transferred, and then one cycle of SPCLK has passed after the last bit was captured.
transfers. This is because change is not enabled when the slave selection pin freezes data in its peripheral reg-
ister and the <SPH> bit is logical 0.
slave device between individual data transfers. When the continuous transfer is completed, the SPFSS pin
will return to the idle state when one cycle of SPCLK has passed after the last bit is captured.
With this setting <SPO>="0", during the idle period:
If the SSP is enabled and valid data exists in the transmit FIFO, the SPFSS master signal driven by "Low"
When a half of the SPCLK period has passed, valid master data is transferred to the SPDO pin. Both the mas-
In the single transfer, the SPFSS line will return to the idle "High" state when all the bits of that data
However, for continuous transfer, the SPFSS signal must be pulsed at HIGH between individual data word
Therefore, to enable writing of serial peripheral data, the master device must drive the SPFSS pin of the
・ The SPCLK signal is set to "Low".
・ SPFSS is set to "High".
・ The transmit data line SPDO is set to "Low".
Page 443
TMPM362F10FG