TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 321

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

4-1
0
Bit
SrcPeripheral
[3:0]
E
Note 1: When you selected Memory-to-Memory, hardware start triggered by DMA is not supported. Transfer is star-
Note 2: Refer to Table 9-3 for the peripheral number of DMA request.
Bit Symbol
ted by writing <E>= 1.
R/W
R/W
Type
Transfer source peripheral (Note2)
0000Å`1111
This is a DMA request peripheral number in binary.
This setting will be ignored if memory is specified as the transfer source.
Channel enable
0 : Disable
1 : Enable
This bit is used to enable or disable the channel. (When memory to memory transfer is set, this bit oper-
ates as a transfer start bit.)
When total number of transfers of DMACCxControl register is complete (the value becomes 0), the corre-
sponding channel is automatically cleared.
If the channel is disabled during a transfer, the data in the channel of FIFO will be lost. To re-start the trans-
fer, all channels must be initialized to reset.
To stop DMA transfer temporarily, use the <Halt> bit to disable DMA requests. Poll the <Active> bit until it be-
comes 0, and then clear the <E> bit to disable the channel.
Page 297
Description
TMPM362F10FG