TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 440

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

12.16
Operation in Each Mode
12.16.1.3
(1)
Transmit and Receive (Full duplex)
SCLK Output Mode
・ If SCxMOD2<WBUF> is set to "0" and the double buffers are disabled
・ If SCxMOD2<WBUF> is set to "1" and the double buffers are enabled
rupt is generated. Concurrently, 8 bits of data written to the transmit buffer are outputted
from the TXD pin, the INTTXx transmit interrupt is generated when transmission of all da-
ta bits has been completed. Then, the SCLK output stops.
ceive buffer and the next transmit data is written to the transmit buffer by the CPU. The or-
der of reading the receive buffer and writing to the transmit buffer can be freely deter-
mined. Data transmission is resumed only when both conditions are satisfied.
the INTRXx interrupt is generated. While 8 bits of data is received, 8 bits of transmit data
is outputted from the TXD pin. When all data bits are sent out, the INTTXx interrupt is gen-
erated and the next data is moved from the transmit buffer to the transmit shift register.
(SCxMOD2<TBEMP> = 1) or when the receive buffer is full (SCxMOD2<RBFULL> =
1), the SCLK output is stopped. When both conditions, receive data is read and transmit da-
ta is written, are satisfied, the SCLK output is resumed and the next round of data transmis-
sion and reception is started.
SCLK is outputted when the CPU writes data to the transmit buffer.
Subsequently, 8 bits of data are shifted into receive buffer and the INTRXx receive inter-
The next round of data transmission and reception starts when the data is read from the re-
SCLK is outputted when the CPU writes data to the transmit buffer.
8 bits of data are shifted into the receive shift register, moved to the receive buffer, and
If the transmit buffer has no data to be moved to the transmit buffer
Page 416
TMPM362F10FG