STLC5465B STMicroelectronics, STLC5465B Datasheet
STLC5465B
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STLC5465B Summary of contents
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... MEMORY . PQFP160 PACKAGE BOUNDARY SCAN FOR TEST FACILITY November 1999 DESCRIPTION The STLC5465B is a Subscriberline interfacecard controller for Central Office, Central Exchange, NT2 and PBX capable of handling : - 16 U Interfaces Megabits line interface cards SLICs (Plain Old Telephone Service Mixed analogue and digital Interfaces (SLICs or ...
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... STLC5465B TABLE OF CONTENTS I - PIN INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 I.1 - Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.2 - Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I.3 - Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 I.3.1 - Input Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 I.3.2 - Output Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 I.3.3 - Input/OutputPin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 III - FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 III.1 - The Switching Matrix KBits III.1.1 - Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 III.1.2 - Architecture of the Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 III ...
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... IV.1 - Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 IV.2 - Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 IV.3 - Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 44 IV.4 - TTL Input DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 IV.5 - CMOS Output DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 44 IV.6 - Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLOCK TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 V.1 - Synchronization Signals delivered by the system . . . . . . . . . . . . . . . . . . . . . . . 45 V.2 - TDM Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 V.3 - GCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 V Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 STLC5465B Page 3/101 ...
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... STLC5465B TABLE OF CONTENTS (continued MEMORY TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 VI.1 - Dynamic Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 VI.2 - Static Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 VII - MICROPROCESSOR TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 VII.1 - ST9 Family MOD0=1, MOD1=0, MOD2 VII.2 - ST10/C16x mult. A/D, MOD0 = 1, MOD1 = 0, MOD2 = VII.3 - ST10/C16x demult. A/D, MOD0 = 1, MOD1 = 0, MOD2 = VII.4 - 80C188 MOD0=1, MOD1=1, MOD2 VII.5 - 80C186 MOD0=1, MOD1=1, MOD2 VII ...
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... IX.5 - Receive Command / Indicate Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 IX.5.1 - Receive Command / Indicate Interrupt when TSV = IX.5.2 - Receive Command / Indicate Interrupt when TSV = IX.6 - Receive Monitor Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 IX.6.1 - Receive Monitor Interrupt when TSV = IX.6.2 - Receive Monitor Interrupt when TSV = PQFP160 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 STLC5465B Page 5/101 ...
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... STLC5465B LIST OF FIGURES I - PIN INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 1 : General Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 III - FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 2 : Switching Matrix Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 3 : Unidirectional and Bidirectional Connections . . . . . . . . . . . . . . . . . . . . . . 17 Figure 4 : Loop Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 5 : Variable Delay through the matrix with ITDM = Figure 6 : Variable Delay through the matrix with ITDM = Figure 7 : Constant Delay through the matrix with ...
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... Figure 48 : 80C188 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 49 : 80C188 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 50 : 80C186 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 51 : 80C186 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 52 : 68000 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 53 : 68000 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 54 : 68020 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 55 : 68020 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 56 : Token Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 57 : Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 STLC5465B Page 7/101 ...
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... STLC5465B I - PIN INFORMATION I.1 - Pin Connections 1 NRESET 2 XTAL1 3 XTAL2 4 WDO VCXO IN 8 VCXO OUT 9 DCLK 10 CLOCKA 11 CLOCKB 12 FRAMEA 13 FRAMEB FSCG 18 FSCV 19 PSS 20 DIN0 21 DIN1 22 DIN2 23 DIN3 24 DIN4 25 DIN5 26 DIN6 27 DIN7 28 DIN8 DOUT0 32 DOUT1 33 DOUT2 34 DOUT3 35 DOUT4 36 DOUT5 37 DOUT6 38 DOUT7 39 NDIS 40 NTRST ...
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... Type : I1 = Input TTL ; Pull- Output CMOS 4mA ; O4T = O4 + Tristate ; O8D = Output CMOS 8mA, Open Drain ; O8T = Output CMOS 8mA, Tristate I1 and I3 must be connected to VDD and VSS if not used STLC5465B Function = 32000kHz can be applied to this input (or one pin Min < f < +50.10 . ...
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... STLC5465B I - PIN INFORMATION (continued) I.2 - Pin Description (continued) Pin N Symbol Type TIME DIVISION MULTIPLEXES (TDM) 20 DIN0 I1 TDM0 Data Input 0 21 DIN1 I1 TDM1 Data Input 1 22 DIN2 I1 TDM2 Data Input 2 23 DIN3 I1 TDM3 Data Input 3 24 DIN4 I1 TDM4 Data Input 4 25 DIN5 ...
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... Type : I1 = Input TTL ; Pull- Output CMOS 4mA ; O4T = O4 + Tristate ; O8D = Output CMOS 8mA, Open Drain ; O8T = Output CMOS 8mA, Tristate STLC5465B Function Hysteresis ; Pull- Output CMOS 8mA, ”1” and ”0” at Low Impedance ; O8DT = Output CMOS 8mA, Open Drain or Tristate ; ...
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... STLC5465B I - PIN INFORMATION (continued) I.2 - Pin Description (continued) Pin N Symbol Type MICROPROCESSOR INTERFACE (continued) 100 D9 I/O Data bit 9 for P if not multiplexed 101 D10 I/O Data bit 10 for P if not multiplexed 102 D11 I/O Data bit 11 for P if not multiplexed 103 ...
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... CMOS output. I.3.3 - Input/Output Pin Definition I/O : Input TTL/ Output CMOS 8mA. N.B. XTAL1 : this input is CMOS. XTAL2 : NTEST pin at 0 has no effect on this pin. STLC5465B Function Hysteresis ; Pull- Output CMOS 8mA, ”1” and ”0” at Low Impedance ; O8DT = Output CMOS 8mA, Open Drain or Tristate ; ...
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... STLC5465B II - BLOCK DIAGRAM The top level functionalities of Multi-HDLC appear on the general block diagram. Figure 1 : General Block Diagram B CLOCK B FRAME A CLOCK A FRAME DOUT7 DOUT6 DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0 NDIS DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 There are : - The switching matrix, ...
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... An additional pin (PSS) permits the generation of a programmable signal composed of 256 bits per frame at a bit rate of 2048 kbit/s. STLC5465B An external pin (NDIS) asserts a high impedance on all the TDM outputs of the matrix when active (during the initialization of the board for example). ...
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... STLC5465B III - FUNCTIONAL DESCRIPTION (continued) Figure 2 : Switching Matrix Data Path DIN 0/7 BIT SYNCHRO ’ HDLC GCI D4/5 HDLCM 1 PRSG LOOP 1 PSEUDO RANDOM DATA A IMTD MEMORIES 64kb/s and Sequence n x 64kb/s Integrity D CM INS D4/5 Tx GCI D7 GCIR 1 D0/7 BIT SYNCHRO OR DOUT 0/7 ...
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... In the sequence integrity mode ( bit located in the Connection Memory), the input time slots are put out 2 frames later (fig page 19). In this case, the delay is defined by a single expression : Constant Delay = (32 - ITSx OTSy So, the delay in sequence integrity mode varies from time slots. STLC5465B 17/101 ...
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... STLC5465B III - FUNCTIONAL DESCRIPTION (continued) Figure 5 : Variable Delay through the matrix with ITDM = OTS y > ITS the n Va ria ble OTS y - ITSx Time ITS0 ITS x ITS x+1 ITSx+2 Inpu t Fra > OTS 0 Outpu t Fra m e Variable De lay (OTS y - ITSx ITS x OTS y ITS the n Variab ITS Tim eS lots ...
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... Case : If OTSy < ITSx, then Variable Delay (ITSx - OTSy) TimeSlots Frame n ITS0 ITSx Input Frame y < x OTS0 Output Frame OTSy Variable Delay : 32 - (ITSx - OTSy) TimeSlots Frame ITS31 ITS0 Frame ITS31 ITS0 ITSx OTSy 32 TimeSlots Frame ITS31 ITS0 ITSx OTSy 32 TimeSlots STLC5465B ITS31 OTS31 ITS31 OTS31 ITS31 OTS31 19/101 ...
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... STLC5465B III - FUNCTIONAL DESCRIPTION (continued) Figure 7 : Constant Delay through the matrix with Delay = (32 -ITSx OTS y ITS : Input Time S lot OTS : Output TimeS lot Frame n ITS0 ITS31 ITS0 Min. Consta nt Delay = 33TS 1 + Max. Consta nt Delay = 95 Time Slots (32 - ITSx) 20/101 Frame Frame ITS31 ...
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... Register (SMCR) has been already written by the microprocessor possible to access to the con- nection memory from microprocessor with the help of two registers : STLC5465B - Connection Memory Data Register (CMDR) and - Connection Memory Address Register (CMAR). III.1.6.3 - Access to Data Memory To extract the contents of the data memory it is ...
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... STLC5465B III - FUNCTIONAL DESCRIPTION (continued) Figure 8: Downstream Switching at 32kb/s 3 DIN0 a din2 dout2 d dout4 Internal command d If SW0=1 DOUT4 (GCI 0) C dout 4 DOUT 4 (GCI 0) dout 2 DOUT2 Internal commands dout 5 DOUT 5 (GCI 1) dout 3 DOUT3 MULTI HDLC STLC 546 5 22/101 Free c Free MON MON ...
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... Free DOUT0 DOUT 0 DOUT6 DOUT1 MULTI HDLC MON GCI 0 B1 GCI GCI 0 B2 GCI Free Free Free GCI 0 DIN4 Internal loopback and 4 bit shifting (2+2) by software DIN6 Switching at 32 kb/s DIN5 STLC 5465 STLC5465B D C GCI1 GCI1 e From DOUT6 GCI1 23/101 ...
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... STLC5465B III - FUNCTIONAL DESCRIPTION (continued) Figure 10: Upstream and Downstream Switching at 16kb/s TDM side D11 D12 D21 D22 TSy D31 D32 D41 D42 TSy of any TDM can be programmable with y comprised between 0 and 31 . 24/101 GCI side D11 D12 16n D21 D22 16n D31 ...
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... Data bytes with bit stuffing - Frame Check Sequence: CRC with polynomial G( Closing Flag. DOUT 6 Direct HDLC Output From Output 6 of the Matrix Conte ntion To Input 7 of the Matrix Bus TIME SLOT ASSIGNER 32 CSMA-CR Echo 32 Tx HDLC 32 Tx FIFO’ DMAC RAM INTERFACE STLC5465B 25/101 ...
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... STLC5465B III - FUNCTIONAL DESCRIPTION (continued) III.2.1.3 - Description and Functions of the HDLC Bytes - FLAG The binary sequence 01111110marks the begin- ning and the end of the HDLC Frame. Note : In reception, three possible flag configura- tions are allowed and correctly detected : - two normal consecutive flags : ...0111111001111110... - two consecutive flags with a ” ...
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... The main information contained in the Descriptor is the address of the Data Buffer, its length and the address of the next Descriptor; so the descriptors can be linked together. STLC5465B This structure allows Store receive frames of variable and unknown length - Read transmit frames stored in external memory by the host - Easily perform the frame relay function ...
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... STLC5465B III - FUNCTIONAL DESCRIPTION (continued) Figure 12 : Structure of the Receive Circular Queue Initial Receive Descriptor NRDA RBA Receive Descriptor n NRDA RBA Receive Buffer n One receive circular queue by channel Figure 13 : Structure of the Transmit Circular Queue Initial Transmit Descriptor NTDA TBA Transmit Descriptor n NTDA ...
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... The channel can be restarted on a START or CONTINUE command. Reception of FLAG (01111110) or IDLE (11111111) between Frames. Address recognition. The microprocessor defines STLC5465B the addressesthat the Rx controller has to take into account. In transparent mode: ”fill character” register se- lected or not. III.2.6.2 - Transmission Control The configuration of the controller operating mode is : HDLC mode or Transparent mode ...
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... STLC5465B III - FUNCTIONAL DESCRIPTION (continued) III.3.2 - GCI and V* Protocol A TDM can carry 8 GCI channels or V* channels. The monitor and S/C bytes always stand at the same position in the TDM in both cases. Channel 0 TS0 TS1 TS2 TS3 B1 B2 MON S/C The GCI or V* channels are composed of 4 bytes and have both the same general structure ...
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... SBV bit of General Configuration Register GCR (02)H on page 68. Downstream. From ISDN channels to GCI chan- nels on page 34 reception: ISDN channel (B1+B2+B transmission: GCI channel (B1+B2+MON+ D+C/ possible to switch the contents of B1, B2 and D channels from 16 “ISDN channels”, TDM side STLC5465B DOUT 5 GCI1 31/101 ...
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... STLC5465B III - FUNCTIONAL DESCRIPTION (continued GCI channels. The contents of B1 and/or B2 can be descram- bled or not. If descrambled the 32 B1/B2 belong to GCI channels mandatory. Receiving six bit word (A, E, S1, S2, S3, S4) from any 16 “ISDN channels”, TDM side. The 16 “six bit word” are stored automatically in the external shared memory ...
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... III - FUNCTIONAL DESCRIPTION (continued) Figure 16: From GCI Channels to ISDN Channels SCRAMBLER SCR by timeslot TDM PCM B1 Mb Microprocessor STLC5465B Extension TX C/I controllers SBV for for the controllers 1 SWITCHING MATRIX RX C/I RX MON controllers controllers for primitives Interrupt controller C/I interrupt Queue, MON interrupt Queue, ...
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... STLC5465B III - FUNCTIONAL DESCRIPTION (continued) Figure 17: From ISDN channels to GCI Channels DESCRAMBLE R TDM PCM at 4 Mb/ s SWITCHING MATRIX B1, B2 (16 bits) ISDN channels III.4 - Microprocessor Interface III.4.1 - Description The Multi-HDLC circuit canbe controlledby several types of microprocessors (ST9, Intel/Motorola data bits interfaces) such as : ...
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... III.4.3 - Definition of the Interface for the differ- ent microprocessors The signals connected to the microprocessor inter- face are presented on the following figures for the different microprocessor. Shared memory From shared memory Read Fetch Fetch Memories Memory microprocessor interface An, [An] To microprocessor Microprocessor STLC5465B Four 35/101 ...
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... STLC5465B III - FUNCTIONAL DESCRIPTION (continued) Figure 18 : Multi-HDLC connected to P with multiplexed buses Multiplex P ST9/10 Address/Data Bus INTEL MOTOROLA INTERFACE 8/16 BITS Figure 19 : Multi-HDLC connected to P with non-multiplexed buses Address Bus P ST10 INTEL MOTOROLA INTERFACE 8/16 BITS Data Bus Figure 20 : Microprocessor Interface for INTEL 80C188 ...
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... NUDS INTERFACE NLDS NAS A1/23 AD8/15 AD0/7 CS0/1, Ax/23 R/NW INT0/1 WDO MHDLC NRESET CS0/1 NDSACK0/1 SIZE0/1 P R/NW INTERFACE NDS NAS A0/23 AD8/15 AD0/7 R/NW CS0/1, Ax/23 INT0/1 WDO MHDLC NRE 0/1 WAIT P R/NW INTERFACE NDS NAS A8/15 AD0/7 STLC5465B 37/101 ...
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... STLC5465B III - FUNCTIONAL DESCRIPTION (continued) III.5 - Memory Interface III.5.1 - Function Description The memory interface allows the connection of Static or Dynamic RAM. The memory space ad- dressable in the two configurationsis not the same. In the case of dynamic memory (DRAM), the mem- ory interface will address Megabytes. In caseof staticmemory(SRAM) only 1 Megabytewill be addressed ...
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... DRAM circuits are : ADM0 bits) corresponding with A1/18 128K x 8 circu it delivered by the P. Figure 27 : 256K x 16 DRAM Circuit Organization CAS1 7 RAS3 5 RAS2 3 RAS1 RAS0 1 DM8/15 ADM0/8, NWE , connected circuit. STLC5465B 512K x 8 circuit 0 DM0/7 A19 A0 6800 UDS 0 LDS CAS0 ...
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... STLC5465B III - FUNCTIONAL DESCRIPTION (continued) III.5.5 DRAM Signals Signals A22 A20 A0 NRAS3 1 1 NRAS2 1 0 NRAS1 0 1 NRAS0 0 0 NCAS1 1 NCAS0 0 The Address bits delivered by the Multi-HDLC for DRAM circuits are : ADM0 bits) correspondingwith A1/20 delivered by the P. Figure DRAM Circuit Organization ...
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... VCXO. Two external pins are needed to perform this func- tion : VCXO-IN and VCXO-OUT (see Figure 32 on Page 42). INT1 Clock La ck Dete ction from CLOCK Frame ADAPTATION Clock Clock HCL SYN1 S YN0 (CSD inte rnal MHDLC STLC5465B FSCV* FSCGCI DCLK 41/101 ...
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... STLC5465B III - FUNCTIONAL DESCRIPTION (continued) Figure 32 : VCXO Frequency Synchronization VCXO 360kHz or 16384kHz VCXO 153 60kHz 163 84kHz III.8 - Interrupt Controller III.8.1 - Description Three external pins are used to manage the inter- rupts generated by the Multi-HDLC . The interrupts have three main sources : - The operating interrupts generated by the HDLC receivers/transmitters, the CI receivers and the monitor transmitters/receivers ...
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... In the reverse case, the WDO signal could be used to reset the board a second time. The FS signal (8kHz) divided by two or the XTAL1 signal (typically 32768kHz) divided by 8192 can be selected to increment the counter. At reset the watchdog is incremented by the XTAL1 signal. STLC5465B IBA + 256 IBA + 256 + HDLC + HDLC MON (Rx) ...
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... STLC5465B The values indicated in the tables from pag pag. 67 are referred to V specificated SPECIFICATIONS IV.1 - Absolute Maximum Ratings Symbol Parameter V 5V Power Supply Voltage DD Input or Output Voltage T Storage Temperature stg IV.2 - Power Dissipation Symbol Parameter P Power Dissipation IV.3 - Recommended DC Operating Conditions ...
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... Duration of FSCG t1 t5l CGI Bit5 Bit6 Bit7 Bit0 Time S lot 31 Time S lot 0 t6 Min. Typ. 239 (320) 244 (325) 249 (330) 120 (158) 122 (162) 125 (165 125000 - (t1 - 10) 75 100 488 STLC5465B 1 Bit1 Max. Unit ns ns +60 ns t1-10 ns t1-10 ns 125 % ns 45/101 ...
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... STLC5465B V - CLOCK TIMING (continued) V.2 - TDM Synchronization Figure 35 : Synchronization Signals received by the Multi-HDLC CLOCK A ( DCLK delivered by the Multi-HDLC FS delivered by the Multi-HDLC DOUT0/7, CB Bit 7, Time Slot 31 DIN0/8 ECHO The four Multiplex Configuration Registers are at zero (no delay between FS and Multiplexes). Symbol Parameter t1 DCLK Clock Period if 4096kHz (3072) ...
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... DCLK Clock Period if 2048kHz (1536) t3 DCLK to FSCG t5 Duration FS t6 DCLK to Data 50pF DCLK to Data 100pF t7 Set-up Time Data/DCLK t7 Hold Time Data/DCLK 125 s CH1 CH7 B2 MON D C Bit 0, Time S lot Min. Typ. Max. Id CLOCK A 244 (325) Id CLOCK 488 (651 244 125000-244 20 20 STLC5465B Unit 100 47/101 ...
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... STLC5465B V - CLOCK TIMING (continued) V Interface Figure Synchronization Signal delivered by the Multi-HDLC ived Multi-HDLC CH0 DIN4/5 DOUT4/5 GCI DCLK de livere Multi-HDLC FSCV* de live Multi-HDLC DOUT0/ FSCG is conne cte DIN0 four Multiple x Configura tion Re giste ( twe Multiple Symbol Parameter t1 Clock Period 4096kHz t3 DCLK to FSCV* ...
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... Delay between NCAS Falling Edge and NCAS rising Edge Tz Delay between NCAS Rising Edge and end of cycle Ts Set-up Time Data /NCAS Rising Edge Th Hold Time Data/NCAS Rising Edge Total Re ad Cycle Tv ach s ignal from the MHDLC is high Min. 2 3.3V DD 1/f 1 STLC5465B 1 Typ. Max. Unit 2 49/101 ...
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... STLC5465B VI - MEMORY TIMING (continued) Figure 39 : Dynamic Memory Write Signals from the Multi-HDLC NDS fro (or equivalent) a MASTE RCLOCK a pplied to XTAL1 P in NRAS0/3 HZ NCAS0/1 NWE ADM0/10 Td DM0/15 NOE impe dance outside this time if MBL = 0 MBL Definition Symbol Parameter Masterclock Frequency Tu Delay between beginning of cycle and NRAS Falling Edge ...
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... NOE width Ts Set-up Time Data /NOE Rising Edge Th Hold Time Data /NOE Rising Edge Tota l Rea d Cycle a a Twz Ts Th Each s igna l de livere d by the MHDLC is high impeda nce outside this time Min. 2 3. STLC5465B 1 Typ. Max. Unit 4 51/101 ...
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... STLC5465B VI - MEMORY TIMING (continued) Figure 41 : Static Memory Write Signals from the Multi-HDLC NDS from P T (or equivalent) a MASTERCLOCK applied to XTAL1 Pin ADM0/18 HZ NCE0/7 NWE NOE DM0/15 HZ Note : See MBL Definition Symbol Parameter T Delay between Data Strobe delivered by the P and beginning of cycle 1/f ...
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... Hold Time Address / NAS t7 Data Valid after Ready t8 Data Valid after Data Strobe (30pF) t9 Set-up Time R/W /NAS t10 Hold Time R/W / Data Strobe t11 Width NDS when immediate access t12 Delay NDS / NCS t12 t11 Min STLC5465B D0/7 t10 Typ. Max. Unit 53/101 ...
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... STLC5465B VII - MICROPROCESSOR TIMING (continued) Figure 43 : ST9 Write Cycle NCS0/1 READY t4 NAS/ ALE NDS/ NRD t5 AD0/7 A0/7 R/W / NWR Symbol Parameter t1 Delay Ready / Chip Select (if t3 > t1), (30pF) Delay when immediate access t2 Hold Time Chip Select / Data Strobe t3 Delay Ready / NAS (if t1 > t3), (30pF) ...
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... Width ALE t5 Set-up Time Address / ALE t6 Hold Time Address /ALE t7 Data valid after ready t8 Data bus at high impedance after NRD (30pF) t9 Set-up Time NBHE, Address A 16/23/ALE t10 Hold Time NBHE / NRD t12 Delay NRD / NCS STLC5465B t12 t7 t8 t10 Min. Typ. Max ...
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... STLC5465B VII - MICROPROCESSOR TIMING (continued) Figure 45 : ST10 (C16x) Write Cycle; Multiplexed A/D NCS0/1 NDSACK0/ NDTAC K / NREADY ALE ND S/ NRD t5 A0/15 AD0/15 R/W / NWR t9 NBHE A16/23 Symbol Parameter t1 Delay Not Ready/ALE (if NCS0/1 = 0), (30pF) Delay when immediate access t2 Hold Time Chip Select / NWR ...
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... Delay when immediate access t4 Width ALE t7 Data valid after NOTREADY falling efge (30pF) t8 Data bus at high impedance after NRD (30pF) t9 Set-up Time NBHE, Address AD0/15, A16/ALE t10 Hold Time NBHE / Address ADO/15, A16/23/NRD t12 Delay NRD / NCS STLC5465B t12 t7 t8 t10 Min. Typ. Max ...
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... STLC5465B VII - MICROPROCESSOR TIMING (continued) Figure 47 : ST10 (C16x) Write Cycle; Demultiplexed A/D NCS0/1 NDSACK0/ DTACK / NREADY ALE ND S/ NRD D0/15 R/W / NWR t9 AD0/15 Symbol Parameter t1 Delay Not Ready/NWR (if NCS0/1 = 0), (30pF) Delay when immediate access t2 Hold Time Chip Select / NRD t3 Delay Not Ready / NWR rising edge ...
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... Delay Ready / ALE (if t1 > t3), (30pF) Delay when immediate access t4 Width ALE t5 Set-up Time Address / ALE t6 Hold Time Address / ALE t7 Data Valid after Ready t8 Data Valid after NRD (30pF) t12 Delay NDS / NCS t12 D0/7 Min STLC5465B Typ. Max. Unit 108 108 59/101 ...
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... STLC5465B VII - MICROPROCESSOR TIMING (continued) Figure 49 : 80C188 Write Cycle NCS0/1 READY t4 NAS /ALE NDS /NRD t5 AD0/7 A0/7 R/W / NWR Symbol Parameter t1 Delay Ready / Chip Select (if t3 > t1), (30pF) Delay when immediate access t2 Hold Time Chip Select / NWR t3 Delay Ready / ALE (if t1 > t3), (30pF) ...
Page 61
... Data Valid after Ready t8 Data Valid after NRD (30pF) t9 Set-up Time NBHE-Address A16/19 / ALE t10 Hold Time Address A1619 / NRD t11 Hold Time NBHE- / NRD t12 Delay NRD / NCS t12 D0/15 t10 NBHE Min 3. 3. STLC5465B t11 Typ. Max. Unit 108 108 61/101 ...
Page 62
... STLC5465B VII - MICROPROCESSOR TIMING (continued) Figure 51 : 80C186 Write Cycle NCS0/1 READY NAS /ALE t4 NDS /NRD t5 AD0/15 A0/15 R/W / NWR t9 NBHE NBHE A16/19 A16/19 Symbol Parameter t1 Delay Ready / Chip Select (if t3 > t1), (30pF) Delay when immediate access t2 Hold Time Chip Select / NWR t3 Delay Ready / ALE (if t1 > ...
Page 63
... Delay NDTACK / NLDS-NUDS Rising Edge t5 Set-up Time Address and R/W / last NLDS-NUDS or NCS t6 Hold Time Address and R/W / NLDS-NUDS t7 Data Valid after NDTACK Falling Edge (30pF) t8 Data High Impedance after NLDS-NUDS Rising Edge (30pF A1/ Min STLC5465B Typ. Max. Unit 98 ns 108 108 63/101 ...
Page 64
... STLC5465B VII - MICROPROCESSOR TIMING (continued) Figure 53 : 68000 Write Cycle NCS0/1 NDTACK NAS/ ALE SIZE0 /NLDS SIZE1 /NUDS A1/23 R/W / NWR D0/15 Symbol Parameter t1 Delay NDTACK / NCS0/1 (if t3 > t1), (30pF) Delay when immediate access t2 Hold Time Chip Select / NLDS-NUDS t3 Delay NDTACK / NLDS-NUDS Falling Edge (if t1> t3), (30pF) ...
Page 65
... Delay when immediate access t4 Delay NDSACK1 / NDS Rising Edge t5 Set-up Time Address and R/W/last NDS or NCS t6 Hold Time Address / NDS t7 Data valid before NDSACK1 falling edge (30pF) t8 Data High Impedance after NDS (30pF Min STLC5465B Typ. Max. Unit 98 ns 108 108 65/101 ...
Page 66
... STLC5465B VII - MICROPROCESSOR TIMING (continued) Figure 55 : 68020 Write Cycle NCS0/1 NDSACK0/ NDTACK NDSACK1/ READY NAS / ALE NDS /NRD SIZE0/ NLDS SIZE1/ NUDS A 0/23 R/W / NWR t9 D0/15 Symbol Parameter t1 Delay NDTACK / NCS0/1 (if t3 > t1), (30pF) Delay when immediate access t2 Hold Time Chip Select / NDS rising edge t3 Delay NDSACK1 / NDS Falling Edge (if t1> ...
Page 67
... Mode fundamental c) Resonance parallel d) Load Capacity Cl = 20pF in accordance with 2 capacitors (33 pF each of them) e) Serial resistor 40 Ohms max N not necessary to add an external bias resistor between XTAL1 pin and XTAL2 pin. This resistor is inside the circuit. STLC5465B Max. Unit MHz Max. Unit 33 MHz 33 ...
Page 68
... STLC5465B VIII - INTERNAL REGISTERS ‘Not used’ bits (Nu) are accessible by the microprocessor but the use of these bits by software is not recommended. ‘Reserved’ bits are not implemented in the circuit. However not recommended to use this address. VIII.1 - Identification and Dynamic Command Register - IDCR (00)H ...
Page 69
... AFAB = 1, the advance of Frame A Signal and Frame B Signal is 0.5 bit time versus the signal frame A (or B) drawn in Figure 34. AFAB = 0, Frame A Signal and Frame B Signal are in accordance with the clock timing (see : Synchronization signals delivered by the Figure 45). Signal applied on FRAMEA/B inputs STLC5465B 69/101 ...
Page 70
... STLC5465B VIII - INTERNAL REGISTERS (continued) MBL : Memory Bus Low impedance MBL = 1, the shared memory bus is at low impedance between two memory cycles. The memory bus includes Control bits, Data bits, Address bits. One Multi-HDLC is connected to the shared memory. MBL = 0, the shared memory bus is at high impedance between two memory cycles. ...
Page 71
... After reset (0000) H bit8 bit7 After reset (0000 7), delayed or not. i 7), delayed or not. 7). STEP for each Output Multiplex 0/7 delayed or not i 7). i 7). bit8 bit7 ME SGC SAV After reset (0000) H STLC5465B bit 0 bit 0 bit 0 SGV TS1 TS0 IMTD 71/101 ...
Page 72
... STLC5465B VIII - INTERNAL REGISTERS (continued) TS0 : Tristate 0 TS0 = 1, the DOUT0/3 and DOUT6/7 pins are tristate : ”0” low impedance, ”1” low impedance and the third state is high impedance. TS0 = 0, the DOUT0/3 and DOUT6/7 pins are open drain : ”0” low impedance, ”1” high impedance ...
Page 73
... DIN3 is used to receive internally TDM1(DIN1) and to shift it (4 bit-times)DOUT3 is used to multiplex internally TDM3 and TDM5. Downstream switching at 32 kb/s on page 22. SW1=0 DIN0 receive 32 (or 24) channels at 64 Kbit (or 48) channels at 64 Kbit/s depending on DR04 bit. STLC5465B CLOCKA/B signal frequency HCL = 0 HCL = 1 4096KHz ...
Page 74
... STLC5465B VIII - INTERNAL REGISTERS (continued) VIII.8 - Connection Memory Data Register - CMDR (0E)H CONTROL REGISTER (CTLR) bit15 SCR PS PRSA S1 S0 OTSV LOOP This 16 bit register is constituted by two registers : SOURCE REGISTER (SRCR) and CONTROL REGISTER (CTLR) SOURCE REGISTER (SRCR) has two use modes depending on CM (bit of CMAR). ...
Page 75
... D channel of GCI 4 in bit 1/2 bit 1 channel of GCI 4 bit 3 channel of GCI 5 D channel of GCI 5 in bit 3/4 D channel of GCI 6 in bit 5/6 bit 5 channel of GCI6 D channel of GCI 7 in bit 7/8 bit 7 channel of GCI 7 STLC5465B Downstream GCI channels DOUT4 DOUT4. DOUT5. DOUT5. 75/101 ...
Page 76
... STLC5465B VIII - INTERNAL REGISTERS (continued) TABLE: SWITCHING AT 16KB/S when ITS3 = ITS 3 ITS 2 ITS 1 ITS 0 Source: D channels of one of 16 Destination: two bits of one TDM The contents of D channels of GCI multiplex DIN4 are transferred into the output timeslot of one TDM defined by the destination register ...
Page 77
... OM0 OTS4 OTS3 OTS2 OTS1 OTS0 After reset (0800 DIN pin OM2 (bit7) OM1(bit6) DIN0 0 0 DIN2 0 1 DIN4 1 0 DIN6 1 1 ITS1 ITS0 IMO (bit1) (bit0) (bit5 STLC5465B bit 0 DOUT pin DOUT0 DOUT2 DOUT4 DOUT6 Input timeslot number 77/101 ...
Page 78
... STLC5465B VIII - INTERNAL REGISTERS (continued) The OTS4/0 and OM0 bits of Destination Register (DSTR of CMAR) indicate the output timeslot number. (OM0 bit is the Least Significant Bit; it indicates either even timeslot or odd timeslot OTS4 OTS3 OTS2 (bit4) (bit3) (bit2 Nota Bene: - CLOCK A MHz in accordance with HCL bit of General Configuration Register GCR (02). ...
Page 79
... READ = 1, Read Time slot Assigner Memory. READ = 0, Write Time slot Assigner Memory. TS0/4 : TIME SLOTS0/4 These five bits define one of 32 time slots in which a channel is set-up or not. bit8 bit7 After reset (0000 stays at its maximum value. H bit8 bit7 Nu HDI After reset (0100) H STLC5465B bit bit 79/101 ...
Page 80
... STLC5465B VIII - INTERNAL REGISTERS (continued) HDI : HDLC INIT HDI = 1, TSA Memory, Tx HDLC, Tx DMA, Rx HDLC, Rx DMA and GCI controllers are reset within 250ms. An automate writes data from Time slot Assigner Data Register (TADR) (except CH0/4 bits) into each TSA Memory location. If the microprocessor reads Time slot Assigner Memory after HDLC INIT, CH0/4 bits of Time slot Assigner Data Register are identical to TS0/4 bits of Time slot Assigner Address Register ...
Page 81
... CSMA = 1, CB output and the Echo Bit are taken into account during this channel transmission by the Tx HDLC. CSMA = 0, CB output and the Echo Bit are defined by V11 (see ” Time slot Assigner Data Register TADR (16)H”). bit8 bit7 Nu CF PEN CSMA NCRC F After reset (0000) H Commands Bits Transmission Mode STLC5465B bit 81/101 ...
Page 82
... STLC5465B VIII - INTERNAL REGISTERS (continued) PEN : CSMA PENALTY significant if CSMA = 1 PEN = 1, the penalty value transmitter which has transmitted a frame correctly will count (PRI +1) logic one received from Echo pin before transmitting next frame. (PRI, priority class given by the buffer descriptor related to the frame. ...
Page 83
... AF8/ all ”1” The value of the first received byte must be equal either to that of AF0 ”1” and the value of the second received byte must be equal either to that of AF8/ all ”1”s. STLC5465B Conditions to Receive a Frame 83/101 ...
Page 84
... STLC5465B VIII - INTERNAL REGISTERS (continued) VIII.15 - Address Field Recognition Address Register - AFRAR (1C)H bit15 CH4 CH3 CH2 CH1 CHO READ The write operation is lauched when AFRAR is written by the microprocessor. AMM : Access to Mask Memory. AMM=1, Access to Address Field Recognition Mask Memory. AMM=0, Access to Address Field Recognition Memory. ...
Page 85
... TDM5 GCI CHANNEL 0 After reset (0000) H bit8 bit7 TDM5 GCI CHANNEL 2 After reset (0000) H bit8 bit7 TDM5 GCI CHANNEL 4 After reset (0000) H bit8 bit7 TDM5 GCI CHANNEL 6 After reset (0000) H STLC5465B bit 0 TDM4 bit 0 TDM4 bit 0 TDM4 bit 0 TDM4 85/101 ...
Page 86
... STLC5465B VIII - INTERNAL REGISTERS (continued) VIII.22 - Transmit Command / Indicate Register - TCIR (2A)H bit15 D G0 CA2 CA1 CA0 READ When this register is written by the microprocessor, these different bits mean : READ : READ C/I MEMORY READ = 1, READ C/I MEMORY. READ = 0, WRITE C/I MEMORY. CA 0/2 : TRANSMIT COMMAND/INDICATE MEMORY ADDRESS CA 0/2 : These bits define one of eight Command/Indicate Channels ...
Page 87
... When this bit is at ”0”, the command written previously by the microprocessor has not yet been executed. Primitive Status bit8 bit7 TIV FABT After reset (000F) H bit8 bit7 ABT STLC5465B bit 0 L NOB 0 Nu bit 0 L NOBT EXE IDLE 87/101 ...
Page 88
... STLC5465B VIII - INTERNAL REGISTERS (continued) NOBT : NUMBER OF BYTE which has been transmitted. NOBT = 1, the first byte is transmitting. NOB the second byte is transmitting, the first byte has been transmitted Last byte ; this L bit is the L bit which has been written by the microprocessor. ABT : ABORT ABT=1, the remote receiver has aborted the current message ...
Page 89
... P3 E0/1 : PRIORITY 3 for entity defined by E0/1 P4 E0/1 : PRIORITY 4 for entity defined by E0/1 Entity definition : DMA Controller 0 1 Microprocessor DMA Controller 1 1 Interrupt Controller Tuv 30ns 60ns 90ns 120ns Twz 30ns 60ns 90ns 120ns bit8 bit7 After reset (E4F0) H Entity STLC5465B bit REF 89/101 ...
Page 90
... STLC5465B VIII - INTERNAL REGISTERS (continued) PRIORITY 5 is the last priority for DRAM Refresh if validated. DRAM Refresh obtains PRIORITY 0 (the first priority) automatically when the first half cycle is spent without access to memory. After reset (E400) , the Rx DMA Controller has the PRIORITY 1 H the Microprocessor has the PRIORITY 2 ...
Page 91
... INTFOV = 1, INTERRUPT CONTROLLER has generated an interrupt, it cannot transfer status from DMA and GCI controllers to external memory, its internal fifo is completed. TIM : TIMER TIM = 1, the programmable timer has generated an interrupt. bit8 bit7 ICOV MTX MRX C/IRX HDLC FOV FWAR FOV FWAR After reset (0000 STLC5465B bit 0 91/101 ...
Page 92
... STLC5465B VIII - INTERNAL REGISTERS (continued) PRSR : Pseudo Random Sequence Recovered PRSR = 1,the Pseudo Random Sequencetransmitted by the generatorhas been recovered by the analyzer. SFCO : Sequence Fault Counter Overload SFCO = 1, the Fault Counter has reached the value (00FF) VIII.30 - Interrupt Mask Register - IMR (3A)H ...
Page 93
... Receive Descriptor Address (RDA Low) Not used TDA High Transmit Descriptor Address (TDA Low) Not used RDA High Receive Descriptor Address (RDA Low) Not used TDA High Transmit Descriptor Address (TDA Low) Not used RDA High Receive Descriptor Address (RDA Low) STLC5465B bit0 93/101 ...
Page 94
... STLC5465B IX - EXTERNAL REGISTERS (continued) IX.2 - Receive Descriptor This receive descriptor is located in shared memory. The quantity of descriptors is limited by the memory size only RDA+00 IBC EOQ RDA+02 Not used RDA+04 RDA+06 Not used RDA+08 Next Receive Descriptor Address Low (16 bits) RDA+10 FR ABT OVF ...
Page 95
... PRI = 1, if CSMA/CR is validated for this channel, the priority class is 8. PRI = 0, if CSMA/CR is validated for this channel the priority class is 10. (see Register CSMA Number of Bytes to be Transmitted (NBT) CRC PRI TBA High (8 bits) C Transmit Buffer Address Low (16 bits) NTDA High (8 bits) STLC5465B 95/101 ...
Page 96
... STLC5465B IX - EXTERNAL REGISTERS (continued) IX.3.2 - Bits written by the DMAC only CFT : Frame correctly transmitted CFT = 1, the Frame has been correctly transmitted. CFT = 0, the Frame has not been correctly transmitted. ABT : Frame Transmitting Aborted ABT = 1, the frame has been aborted by the microprocessor during the transmission. ...
Page 97
... AIS detected during more 30 ms from any input timeslot and switched to B1, B2 channels (16 bits) of the GCI 1 (DOUT5) in transparent mode or not bit8 bit7 C6/A C5/E C4/S1 C3/S2 C2/S3 C1/S4 Word stored in shared memory outgoing to DOUT4 outgoing to DOUT5 Reserved STLC5465B bit 0 97/101 ...
Page 98
... STLC5465B IX - EXTERNAL REGISTERS (continued This bit defines one of two GCI y (DIN4/DOUT4 or DIN5/DOUT5 GCI0 (DIN4/DOUT4) is the source GCI1 (DIN5/DOUT5) is the source. A2/0 : GCI Channel belonging to GCI 0 or GCI 1. C6/1 : New Primitive received twice consecutively. Case of S0=S1= S1/S4 bits received twice consecutively. Case ...
Page 99
... Byte received once if V* Protocol has been validated. M11/18 : Next new Byte received twice consecutively if GCI Protocol has been validated. This byte is at ”1” in case of V* protocol. T15/0 : Binary counter value when a new primitive is occurred. bit8 bit7 A1 A0 ODD M12 M11 STLC5465B bit 99/101 ...
Page 100
... STLC5465B X - PQFP160 PACKAGE MECHANICAL DATA Millimeters Dimensions Min. Typ 0.25 A2 3.17 3.42 B 0.22 C 0.13 D 30.95 31.20 D1 27.90 28.00 D3 25.35 e 0.65 E 30.95 31.20 E1 27.90 28.00 E3 25.35 L 0.65 0.80 L1 1.60 K 100/101 Inches Max. Min. Typ. 4.07 0.010 3.67 0.125 0.135 0.38 0.009 0.23 ...
Page 101
... The ST logo is a registered trademark of STMicroelectronics 1999 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com STLC5465B 101/101 ...