STLC5465B STMicroelectronics, STLC5465B Datasheet - Page 12

• Manufacturer Part Number: STLC5465B
• Description: Telecom ICs Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom IC - Variousr

Specifications of STLC5465B

• Operating Supply Voltage: 4.75 V to 5.25 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-160
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STLC5465B
I - PIN INFORMATION (continued)
I.2 - Pin Description (continued)
Type : I1 = Input TTL ;
12/101
MICROPROCESSOR INTERFACE (continued)
MEMORY INTERFACE
Pin N
100
101
102
103
104
105
106
109
110
111
112
113
114
115
116
117
118
119
120
123
124
125
126
127
128
129
130
131
132
135
136
137
138
139
O4 = Output CMOS 4mA ;
O8D = Output CMOS 8mA, Open Drain ;
O8T = Output CMOS 8mA, Tristate
NRAS0/NCE0
NCAS0/NCE1
NRAS1/NCE2
NCAS1/NCE3
NRAS2/NCE4
NRAS3/NCE6
Symbol
ADM10
ADM11
ADM12
ADM13
ADM14
NCE5
NCE7
ADM0
ADM1
ADM2
ADM3
ADM4
ADM5
ADM6
ADM7
ADM8
ADM9
NWE
NOE
TRO
D10
D11
D12
D13
D14
D15
TRI
D9
Type
O4T
O4T
O4T
O4T
O4T
O4T
O4T
O4T
O4T
O4T
O8T
O8T
O8T
O8T
O8T
O8T
O8T
O8T
O8T
O8T
O8T
O8T
O8T
O8T
O8T
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O4
I3
I2 = I1 + Pull-up ;
O4T = O4 + Tristate ;
Data bit 9 for P if not multiplexed
Data bit 10 for P if not multiplexed
Data bit 11 for P if not multiplexed
Data bit 12 for P if not multiplexed
Data bit 13 for P if not multiplexed
Data bit 14 for P if not multiplexed
Data bit 15 for P if not multiplexed
Token Ring Input (for use Multi-HDLC s in cascade)
Token Ring Output (for use Multi-HDLC s in cascade)
Write Enable for memory circuits
Control Output Enable for memory circuits
Row Address Strobe Bank 0 / Chip Enable 0 for SRAM
Column Address Strobe Bank 0 / Chip Enable1 for SRAM
Row Address Strobe Bank 1 / Chip Enable 2 for SRAM
Column Address Strobe Bank 1 / Chip Enable 3 for SRAM
Row Address Strobe Bank 2 / Chip Enable 4 for SRAM
Chip Enable 5 for SRAM
Row Address Strobe Bank 3 / Chip Enable 6 for SRAM
Chip Enable 7 for SRAM
Address bit 0 for SRAM and DRAM
Address bit 1 for SRAM and DRAM
Address bit 2 for SRAM and DRAM
Address bit 3 for SRAM and DRAM
Address bit 4 for SRAM and DRAM
Address bit 5 for SRAM and DRAM
Address bit 6 for SRAM and DRAM
Address bit 7 for SRAM and DRAM
Address bit 8 for SRAM and DRAM
Address bit 9 for SRAM and DRAM
Address bit 10 for SRAM and DRAM
Address bit 11 for SRAM only
Address bit 12 for SRAM only
Address bit 13 for SRAM only
Address bit 14 for SRAM only
I3 = I1 + Hysteresis ;
O8 = Output CMOS 8mA, ”1” and ”0” at Low Impedance ;
O8DT = Output CMOS 8mA, Open Drain or Tristate ;
Function
I4 = I3 + Pull-up ;