STLC5465B STMicroelectronics, STLC5465B Datasheet - Page 78

• Manufacturer Part Number: STLC5465B
• Description: Telecom ICs Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom IC - Variousr

Specifications of STLC5465B

• Operating Supply Voltage: 4.75 V to 5.25 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-160
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STLC5465B
VIII - INTERNAL REGISTERS (continued)
The OTS4/0 and OM0 bits of Destination Register (DSTR of CMAR) indicate the output timeslot number.
(OM0 bit is the Least Significant Bit; it indicates either even timeslot or odd timeslot
Nota Bene:
- CLOCK A/B is at 4 or at 8 MHz in accordance with HCL bit of General Configuration Register GCR (02).
The definition of IMCRO/1, OMCRO/1 are kept with bit time = 244 ns
Remarks:
- OM0, bit5 of DSTR indicates either even TDM or odd TDM if TDM at 2 Mb/s.
- OM0, bit5 of DSTR indicates either even Output timeslot or odd Output timeslot if TDM at 4 Mb/s.
- IM0, bit5 of SRCR indicates either even TDM or odd TDM if TDM at 2 Mb/s.
- IM0, bit5 of SRCR indicates either even Output timeslot or odd Output timeslot if TDM at 4 Mb/s.
- CAC = CACL = 0, DSTR is the Address Register of the Connection Memory;
- CAC or CACL = 1, DSTR is used to indicate the current address for the Connection Memory ; its contents
CM = 0, access to data memory (read only) ;
- DSTR is the Address Register of the Data Memory; its contents is assigned to the inputs.
ACCESS MODE REGISTER (AMR)
READ : READ MEMORY
CM
BID
CAC
78/101
HCL=1, bit clock frequency is at 8 192 KHz.
For a TDM at 4 Mbit/s or 2Mbit/s, each received bit is sampled at 3/4 bit-time.
HCL=0, bit clock frequency is at 4 096 KHz
For a TDM at 4 Mbit/s, each received bit is sampled at half bit-time.
For a TDM at 2 Mbit/s, each received bit is sampled at 3/4 bit-time.
is assigned to the outputs.
OTS4
(bit4)
0
0
0
0
1
: CONNECTION MEMORY
: BIDIRECTIONAL CONNECTION
: CYCLICAL ACCESS
READ = 1, Read Connection Memory (or Data Memory in accordance with CM).
READ = 0, Write Connection Memory.
CM = 1, Write or Read Connection Memory in accordance with READ.
CM = 0, Read only Data Memory (READ = 0 has no effect).
BID = 1; Two connections are set up:
BID = 0; One connection is set up:
CAC = 1 (BID is ignored)
if Write Connection Memory, an automatic data write from Connection Memory Data Register
(CMDR) up to 256 locations of ConnectionMemory occurs. The first address is indicated by the
register DSTR, the last is (FF)H.
if Read Connection Memory, an automatic transfer of data from the location indicated by the
register (DSTR) into Connection Memory Data Register (CMDR) after reading by the
microprocessor occurs. The last location is (FF)H.
CAC = 0, Write and Read Connection Memory in the normal way.
ITSx ITDMp ------> OTSy OTDMq (LOOP of CMDR Register is taken into account) and
ITSy ITDMq ------> OTSx OTDMp (LOOP of CMDR Register is not taken into account).
ITSx ITDMp ------> OTSy OTDMq only.
OTS3
(bit3)
0
0
0
0
1
OTS2
(bit2)
0
0
0
0
1
=
OTS1
(bit1)
0
0
0
0
1
OTS0
(bit0)
0
0
1
1
1
OMO
(bit5)
0
1
0
1
1
Output timeslot number
63
0
1
2
3
=