STLC5465B STMicroelectronics, STLC5465B Datasheet - Page 6

• Manufacturer Part Number: STLC5465B
• Description: Telecom ICs Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom IC - Variousr

Specifications of STLC5465B

• Operating Supply Voltage: 4.75 V to 5.25 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-160
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STLC5465B
LIST OF FIGURES
I - PIN INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
II - BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
III - FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
IV - DC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
V - CLOCK TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6/101
Figure 1 : General Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 2 : Switching Matrix Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 3 : Unidirectional and Bidirectional Connections . . . . . . . . . . . . . . . . . . . . . . 17
Figure 4 : Loop Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5 : Variable Delay through the matrix with ITDM = 1 . . . . . . . . . . . . . . . . . . . . 18
Figure 6 : Variable Delay through the matrix with ITDM = 0 . . . . . . . . . . . . . . . . . . . . 19
Figure 7 : Constant Delay through the matrix with SI = 1 . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8: Downstream Switching at 32kb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 9: Upstream Switching at 32kb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10: Upstream and Downstream Switching at 16kb/s . . . . . . . . . . . . . . . . . . . . 24
Figure 11 : HDLC and DMA Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12 : Structure of the Receive Circular Queue . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 13 : Structure of the Transmit Circular Queue . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 14 : D, C/I and Monitor Channel Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 15: GCI channel to/from ISDN Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 16: From GCI Channels to ISDN Channels . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 17: From ISDN channels to GCI Channels . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 17.1: Write FIFO and Fetch Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 18 : Multi-HDLC connected to P with multiplexed buses . . . . . . . . . . . . . . . . . 36
Figure 19 : Multi-HDLC connected to P with non-multiplexed buses . . . . . . . . . . . . . . . 36
Figure 20 : Microprocessor Interface for INTEL 80C188 . . . . . . . . . . . . . . . . . . . . . . 36
Figure 21 : Microprocessor Interface for INTEL 80C186 . . . . . . . . . . . . . . . . . . . . . . 36
Figure 22 : Microprocessor Interface for MOTOROLA 68000 . . . . . . . . . . . . . . . . . . . 37
Figure 23 : Microprocessor Interface for MOTOROLA 68020 . . . . . . . . . . . . . . . . . . . 37
Figure 24 : Microprocessor Interface for ST9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 25 : n x 128K x 16 SRAM Memory Organization . . . . . . . . . . . . . . . . . . . . . . 39
Figure 26 : 512K x 8 SRAM Circuit Memory Organization . . . . . . . . . . . . . . . . . . . . . 39
Figure 27 : 256K x 16 DRAM Circuit Organization . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 28 : 1M x 16 DRAM Circuit Organization . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 29 : 4M x 16 DRAM Circuit Organization . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 30 : Chain of n Multi-HDLC Components . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 31 : MHDLC Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 32 : VCXO Frequency Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 33 : The Three Circular Interrupt Memories . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 34 : Clocks received and delivered by the Multi-HDLC . . . . . . . . . . . . . . . . . . . 45
Figure 35 : Synchronization Signals received by the Multi-HDLC . . . . . . . . . . . . . . . . . 46
Figure 36 : GCI Synchro Signal delivered by the Multi-HDLC . . . . . . . . . . . . . . . . . . . 47
Figure 37 : V* Synchronization Signal delivered by the Multi-HDLC . . . . . . . . . . . . . . . . 48
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