STLC5465B STMicroelectronics, STLC5465B Datasheet - Page 5

• Manufacturer Part Number: STLC5465B
• Description: Telecom ICs Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom IC - Variousr

Specifications of STLC5465B

• Operating Supply Voltage: 4.75 V to 5.25 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-160
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE OF CONTENTS (continued)
VIII - INTERNAL REGISTERS (continued)
IX - EXTERNAL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
X - PQFP160 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
IX.5.1 - Receive Command / Indicate Interrupt when TSV = 0 . . . . . . . . . . . . . . . . . . . 97
IX.6.1 - Receive Monitor Interrupt when TSV = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 98
VIII.27 - Initiate Block Address Register - IBAR (34)H . . . . . . . . . . . . . . . . . . . . . . . 90
VIII.28 - Interrupt Queue Size Register - IQSR (36)H . . . . . . . . . . . . . . . . . . . . . . . . 90
VIII.29 - Interrupt Register - IR (38)H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
VIII.30 - Interrupt Mask Register - IMR (3A)H . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
VIII.31 - Timer Register - TIMR (3C)H
VIII.32 - Test Register - TR (3E)H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
IX.1 - Initialization Block in External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
IX.2 - Receive Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
IX.2.1 - Bits written by the Microprocessor only . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
IX.2.2 - Bits written by the Rx DMAC only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
IX.2.3 - Receive Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
IX.3 - Transmit Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
IX.3.1 - Bits written by the Microprocessor only . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
IX.3.2 - Bits written by the DMAC only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
IX.3.3 - Transmit Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
IX.4 - Receive & Transmit HDLC Frame Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 96
IX.5 - Receive Command / Indicate Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
IX.5.2 - Receive Command / Indicate Interrupt when TSV = 1 . . . . . . . . . . . . . . . . . . . 98
IX.6 - Receive Monitor Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
IX.6.2 - Receive Monitor Interrupt when TSV = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 99
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
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