STLC5465B STMicroelectronics, STLC5465B Datasheet - Page 73

• Manufacturer Part Number: STLC5465B
• Description: Telecom ICs Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom IC - Variousr

Specifications of STLC5465B

• Operating Supply Voltage: 4.75 V to 5.25 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-160
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

VIII - INTERNAL REGISTERS (continued)
DR64 : Data Rate of TDM6 is at 4Mb/s.Case:M1=M0=0
M1/0
SW
SW1 : SW1: Switching at 32 Kbit/s for the TDM1 (DIN1/DOUT1)
M1
0
0
1
1
: Switching at 32 Kbit/s for the TDM0 (DIN0/DOUT0)
: Data Rate of TDM0/8;
SW0=1
DIN0 can receive 64 channels at 32 Kbit/s if Data Rate of TDM0 is at 2048 Kbit/s.
DOUT0 can deliver 64 channels at 32 Kbit/s.
DIN2/DOUT2 are not available.
DIN2 is used to receive internally TDM0 (DIN0) 4 bit-times shifted
DOUT2 is used to multiplex internally TDM2 and TDM4. Downstream switching at 32 kb/s on
page 22.
SW1=1
DIN1 can receive 64 channels at 32 Kbit/s if Data Rate of TDM1is at 2048 Kbit/s.DOUT0 can
deliver 64 channels at 32 Kbit/s.
DIN3/DOUT3 are not available.
DIN3 is used to receive internally TDM1(DIN1) and to shift it (4 bit-times)DOUT3 is used to
multiplex internally TDM3 and TDM5. Downstream switching at 32 kb/s on page 22.
SW1=0
DIN0 receive 32 (or 24) channels at 64 Kbit/s or 64 (or 48) channels at 64 Kbit/s depending on
DR04 bit.
DR64 = 1, the signal received from DIN6 pin and the signal delivered by Dout6 pin are at 4Mb/s.
DIN7 pin and DOUT7 pin are ignored.
The Switching Matrix cannot be used to switch the channels to/from the HDLC controllers but
the RX HDLC controller can be connectedto DIN8 and the TX HDLC controller can be connected
to CB pin.
The Time Division Multiplex 6 is constituted by 64 timeslots numbered from 0 to 63.
DR64 = 0, the signals received from DIN6/7 pins and the signals delivered by Dout6/7 pins are
at 2M b/s.
these two bits indicatethe data rateof heightTime Division Multiplexes TDM0/7 relative to DIN0/7
and DOUT0/7. The table below shows the different data rates with the clock frequency defined
by HCL bit (General Configuration Register).
M0
0
1
0
1
2048 (or 4096 in accordance with DR0x4)
1536 (or 3072 in accordance with DR0x4)
Data Rate of TDM0/7 in Kbit/s
Reserved
Reserved
4096KHz
3072KHz
HCL = 0
CLOCKA/B signal frequency
8192KHz
6144KHz
STLC5465B
HCL = 1
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