STLC5465B STMicroelectronics, STLC5465B Datasheet - Page 76

• Manufacturer Part Number: STLC5465B
• Description: Telecom ICs Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom IC - Variousr

Specifications of STLC5465B

• Operating Supply Voltage: 4.75 V to 5.25 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-160
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STLC5465B
VIII - INTERNAL REGISTERS (continued)
TABLE: SWITCHING AT 16KB/S when ITS3 =1
PRSA : Pseudo Random Sequence analyzer
PS
SCR
76/101
S1
1
S0 ITS 3 ITS 2 ITS 1 ITS 0
0
: Programmable Synchronization
: Scrambler/ Descrambler
If PRSA = 1, PRS analyzer is enabled during OTSy OTDMq and receives data :
INS = 0, data comes from Data Memory.
INS = 1 AND PRSG=1, Data comes from PRS Generator (Test Mode).
If PRSA = 0, PRS analyzer is disabled during OTSy OTDMq.
If PS = 1, Programmable Synchronization Signal Pin is at ”1” during the bit time defined by OTSy
and OTDMq.
For OTSy and OTDMq with y = q = 0, PSS pin is at ”1” during the first bit of the frame defined
by the Frame synchronization Signal (FS).
If PS = 0, PSS Pin is at ”0” during the bit time defined by OTSy and OTDMq.
SCR=1, the scrambler or the descrambler are enabled. Both of them are located after the
switching matrix.
1
1
0
0
1
1
0
1
0
1
4/7 of multiplex DIN4 are transferred
The contents of D channels of GCI 0
4/7 of multiplex DIN5 are transferred
0 /3 of multiplex DIN4 are transferred
into the output timeslot of one TDM
/3 of multiplex DIN5 are transferred
into the output timeslot of one TDM
into the output timeslot of one TDM
The contents of D channels of GCI
The contents of D channels of GCI
into the output timeslot of one TDM
defined by the destination register
defined by the destination register
defined by the destination register
The contents of D channels of GCI
Source: D channels of one of 16
Destination: two bits of one TDM
defined by the destination register
D channel of GCI 0 in bit 7/8
D channel of GCI 1 in bit 5/6
D channel of GCI 2 in bit 3/4
D channel of GCI 3 in bit 1/2
D channel of GCI 4 in bit 7/8
D channel of GCI 5 in bit 5/6
D channel of GCI 6 in bit 3/4
D channel of GCI 7 in bit 1/2
D channel of GCI 0 in bit 7/8
D channel of GCI 1 in bit 5/6
D channel of GCI 2 in bit 3/4
D channel of GCI 3 in bit 1/2
D channel of GCI 4 in bit 7/8
D channel of GCI 5 in bit 5/6
D channel of GCI 6 in bit 3/4
D channel of GCI 7 in bit 1/2
GCI channels
Upstream
(CMAR).
(CMAR).
(CMAR).
(CMAR).
Destination: D channels of one of 16
(same number as the number of the
(same number as the number of the
(same number as the number of the
(same number as the number of the
output timeslot) is transferred in D
output timeslot) is transferred in D
output timeslot) is transferred in D
output timeslot) is transferred in D
The contents of the input timeslot
The contents of the input timeslot
The contents of the input timeslot
The contents of the input timeslot
channel of GCI 0/3 of multiplex
channel of GCI 4/7 of multiplex
channel of GCI 0/3 of multiplex
channel of GCI 4/7 of multiplex
Source: two bits of one TDM
bit 7/8 in D channel of GCI 0
bit 5/6 in D channel of GCI 1
bit 3/4 in D channel of GCI 2
bit 1/2 in D channel of GCI 3
bit 7/8 in D channel of GCI 4
bit 5/6 in D channel of GCI 5
bit 3/4 in D channel of GCI 6
bit 1/2 in D channel of GCI 7
bit 7/8 in D channel of GCI 0
bit 5/6 in D channel of GCI 1
bit 3/4 in D channel of GCI 2
bit 1/2 in D channel of GCI 3
bit 7/8 in D channel of GCI 4
bit 5/6 in D channel of GCI 5
bit 3/4 in D channel of GCI 6
bit 1/2 in D channel of GCI 7
GCI channels
Downstream
DOUT4.
DOUT5.
DOUT5.
DOUT4