STLC5465B STMicroelectronics, STLC5465B Datasheet - Page 90

• Manufacturer Part Number: STLC5465B
• Description: Telecom ICs Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom IC - Variousr

Specifications of STLC5465B

• Operating Supply Voltage: 4.75 V to 5.25 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-160
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STLC5465B
VIII - INTERNAL REGISTERS (continued)
PRIORITY 5 is the last priority for DRAM Refresh if validated. DRAM Refresh obtains PRIORITY 0 (the
first priority) automatically when the first half cycle is spent without access to memory.
After reset (E400)
VIII.27 - Initiate Block Address Register - IBAR (34)H
A8/23 : Address bits. These 16 bits are the segment address bits of the Initiate Block (A8 to A23 for the
The Initiate Block Address (IBA) is :
The 23 more significant bits define one of 8 Megawords. (One word comprises two bytes.)
The least significant bit defines one of two bytes when the microprocessor selects one byte.
Example: MHDLC device address inside P mapping = 100000H
VIII.28 - Interrupt Queue Size Register - IQSR (36)H
CS0/1 : Command/Indicate Interrupt Queue Size
MS0/2 : Monitor Channel Interrupt Queue Size
HS0/2 : HDLC Interrupt Queue Size
90/101
TBFS
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 0 0 0 0 0 0 0 0
bit15
bit15
A23
23
A22
0
Initiate Block address inside P mapping = 110000H
IBAR value = (110000 - 100000)/256= 100H
external memory in the MHDLC address space).The offset is zero (A0 to A7 =”0”).
These two bits define the size of Command/Indicate Interrupt Queue in external memory.
The location is IBA + 256 + HDLC Queue size + Monitor Channel Queue Size (see The Initiate
Block Address (IBA)).
These three bits define the size of Monitor Channel Interrupt Queue in external memory.
The location is IBA + 256 + HDLC Queue size.
These three bits define thesize ofHDLC status InterruptQueue in externalmemory foreach channel.
The location is IBA+256 (see The Initiate Block Address (IBA))
HS2
0
0
0
0
1
1
1
1
A21
0
HS1
H
0
0
1
1
0
0
1
1
, the Rx DMA Controller has the PRIORITY 1
A20
the Microprocessor has the PRIORITY 2
the Tx DMA Controller has the PRIORITY 3
the Interrupt Controller has the PRIORITY 4
the DRAM Refresh has the PRIORITY 5
0
HS0
0
1
0
1
0
1
0
1
A19
0
Queue Size
1024 words
128 words
256 words
384 words
512 words
640 words
768 words
896 words
HDLC
A18
0v
A17
0
After reset (0000)H
After reset (0000)
MS2 MS1 MS0
0
0
0
0
1
1
1
1
A16
bit8
bit8
0d
0
0
1
1
0
0
1
1
HS2
A15
bit7
bit7
0
1
0
1
0
1
0
1
H
HS1
A14
Queue Size
1024 words
128 words
256 words
384 words
512 words
640 words
768 words
896 words
HS0
A13
MON
MS2
A12
CS1
8
MS1
0
0
1
1
A11
7
CS0
0
1
0
1
MS0
A10
Queue Size
128 words
192 words
256 words
CS1
64 words
A9
C/I
CS0
bit 0
bit 0
A8
0