STLC5465B STMicroelectronics, STLC5465B Datasheet - Page 69

• Manufacturer Part Number: STLC5465B
• Description: Telecom ICs Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom IC - Variousr

Specifications of STLC5465B

• Operating Supply Voltage: 4.75 V to 5.25 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-160
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

VIII - INTERNAL REGISTERS (continued)
TSV
EVM
D7
SYN0/1: SYNCHRONIZATION
HCL
CSD
SELB : SELECT B
BSEL : B SELECTED (this bit is read only)
SCL
AFAB : Advanced Frame A/B Signal
: Time Stamping Validated
: EXTERNAL VCXO MODE
: HDLC connected to MATRIX
: HIGH BIT CLOCK
: Clock Supervision Deactivation
: Single Clock
TSV = 1, the time stamping counter becomes a free binary counter and counts down from 65535
to 0 in step of 250ms (Total = 16384ms). So if an event occurs when the counter indicates A and
if the next event occurs when the counter indicates B then : t = (A-B) x 250ms is the time which
haspassedbetweenthe two eventswhich have beenstored in memoryby the InterruptController
(for Rx C/I and Rx MON CHANNEL only).
TSV = 0, the counter becomes a decimal counter.The Timer Register and this decimal counter
constitute a Watch Dog or a Timer.
EVM=1,VCXO Synchronization Counter is divided by 32.
EVM=0,VCXO Synchronization Counter is divided by 30.
D7 = 1, the transmit HDLC is connected to matrix input 7, the DIN7 signal is ignored.
D7 = 0, the DIN7 signal is taken into account by the matrix, the transmit HDLC is ignored by the
matrix.
SYN0/1 : these two bits define the signal applied on FRAMEA/B inputs. For more details, see
”Synchronization signals delivered by the system. V.1.
This bit defines the signal applied on CLOCKA/B inputs.
HCL = 1, bit clock signal is at 8192kHz
HCL= 0, bit clock signal is at 4096kHz
CSD = 1, the lack of selected clock is not seen by the microprocessor; INT1 is masked.
CSD = 0, when the selected clock disappears the INT1 pin goes to 5V, 250ms after this
disappearance.
SELB = 1, FRAME B and CLOCK B must be selected.
SELB = 0, FRAME A and CLOCK A must be selected.
BSEL = 1, FRAME B and CLOCK B are selected.
BSEL = 0, FRAME A and CLOCK A are selected.
This bit defines the signal delivered by DCLK output pin.
SCL = 1, Data Clock is at 2048kHz.
SCL = 0, Data Clock is at 4096kHz.
AFAB = 1, the advance of Frame A Signal and Frame B Signal is 0.5 bit time versus the signal
frame A (or B) drawn in Figure 34.
AFAB = 0, Frame A Signal and Frame B Signal are in accordance with the clock timing
(see : Synchronization signals delivered by the Figure 45).
SYN1
0
0
1
1
SYN0
0
1
0
1
SYIinterface
GCI Interface (the signal defines the first bit of the frame)
Vstar Interface (the signal defines thrid bit of the frame)
Not used
Signal applied on FRAMEA/B inputs
STLC5465B
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