STLC5465B STMicroelectronics, STLC5465B Datasheet - Page 97

• Manufacturer Part Number: STLC5465B
• Description: Telecom ICs Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom IC - Variousr

Specifications of STLC5465B

• Operating Supply Voltage: 4.75 V to 5.25 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-160
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IX - EXTERNAL REGISTERS (continued)
Receiver
Tx
A4/0
ERF
EOQ
HALT : The Receive DMA Controller has received HALT or ABORT (on the outside of frame) from the
BE
CFR
IX.5 - Receive Command / Indicate Interrupt
IX.5.1 - Receive Command / Indicate Interrupt when TSV = 0
Time Stamping not validated (bit of GCR Register)
This word is located in the Command/Indicate interrupt queue ; IQSR Register indicates the size of this
interrupt queue located in the external memory.
NS
S0/S1 Source of the event:
bit15
NS
S1
0
0
0
0
1
1
1
: Tx = 0, Receiver
: Error detected on Received Frame
: End of Queue
: Buffer Filled
: Correctly Frame Received
: New Status.
: Rx HDLC Channel 0 to 31
Nu
An error such as CRC not correct, Abort, Overflow has been detected.
The receive DMA Controller has encountered the current receive Descriptor with EOQ at ”1”.
DMA Controller is waiting ”Continue” from microprocessor.
microprocessor; it is waiting ”Continue” from the microprocessor.
If IBC bit of Receiver Descriptor is at ‘1’, the Receive DMA Controller puts BF at”1” when it has
filled the current buffer with data from the received frame.
A receive frame is ended with a correct CRC. The end ofthe frame islocated in the last descriptor
if several Descriptors.
Before writing the features of event in the external memory the Interrupt Controller reads the
NS bit :
if NS = 0, the Interrupt Controller puts this bit at ‘1’ when it writes the new primitive which has
been received.
if NS = 1, the Interrupt Controller puts INTFOV bit at ‘1’ to generate an interrupt (IR Interrupt
Register).
When the microprocessor has read the status word, it puts this bit at ‘0’ to acknowledge the new
status. This location becomes free for the Interrupt Controller.
S0
0
0
1
1
0
0
1
S1
G0
X
0
1
0
1
0
1
S0
A, E, S1/S4 bits from any input timeslot switched to one timeslot 4n+3 of GCI 0 without
A, E, S1/S4 bits from any input timeslot switched to one timeslot 4n+3 of GCI 1 without
G0
AIS detected during more 30 ms from any input timeslot and switched to B1, B2
AIS detected during more 30 ms from any input timeslot and switched to B1, B2
A2
Primitive C1/6 received from GCI Multiplex 0 corresponding to DIN4
Primitive C1/6 received from GCI Multiplex 1 corresponding to DIN5
channels (16 bits) of the GCI 1 (DOUT5) in transparent mode or not.
channels (16 bits) of the GCI 0 (DOUT4) in transparent mode or not
A1
bit8
A0
Word stored in shared memory
bit7
Nu
outgoing to DOUT4
outgoing to DOUT5
Reserved
Nu
C6/A
C5/E C4/S1 C3/S2 C2/S3 C1/S4
STLC5465B
97/101
bit 0