STLC5465B STMicroelectronics, STLC5465B Datasheet - Page 41

• Manufacturer Part Number: STLC5465B
• Description: Telecom ICs Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom IC - Variousr

Specifications of STLC5465B

• Operating Supply Voltage: 4.75 V to 5.25 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-160
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

III - FUNCTIONAL DESCRIPTION (continued)
III.7 - Clock Selection and Time Synchronization
III.7.1 - Clock Distribution Selection and
Two clock distributions are available: Clock at
4.096 MHz or 8.192 MHz and a synchronization
signal at 8 KHz. The component has to select one
of these two distributions and to check its integrity.
See Fig. 31 MHDLC clock generation.
Two other clock distributions are allowed: Clock at
3072 MHz or 6144 MHz and a synchronization
signal at 8 KHz. See General Configuration Regis-
ter GCR (02)H on page 61 DCLK, FSC GCI and
FSC V* are output on three external pins of the
Multi-HDLC. DCLK is the clock selected between
Clock A and Clock B. FSC, GCI and FSC V* are
functions of the selected distribution and respect
the GCI and V* frame synchronization specifica-
tions.
The supervision of the clock distribution consists of
verifying its availability. The detection of the clock
absence is done in a less than 250 microseconds.
In case the clock is absent, an interrupt is gener-
ated with a 4 kHz recurrence. Then the clock
distribution is switched automatically up to detec-
tion of couple A or couple B. When a couple is
detected the change of clock occurs on a falling
edgeof the new selecteddistribution.Moreover the
Figure 31 : MHDLC Clock Generation
Supervision
FRAME A
CLOCK A
FRAME B
CLOCK B
Select A o r B
(SELB)
REF. CLOCK
FRAME A a nd CLOCK A
CLOCK S ELECTION
GENERAL CONFIGURATION REGISTER (GCR)
A o r B
Se lected
(BS EL)
a re s e lecte d
Deactivation
At RESET
Su pervision
RES ET
(CSD)
Clock
from 2 50 s
Clock La ck
Dete ction
INT1
HCL
clock distribution can be controlled by the micro-
processor thanks to SELB, bit of General Configu-
ration Register.
Depending on the applications, three different sig-
nals of synchronization (GCI, V* or Sy) can be
provided to the component. The clock A/B fre-
quency can be a 4096 or 8192kHz clock. The
component is informed of the synchronization and
clocks that are connected by software.The timings
of the different synchronization are given page 45.
III.7.2 - VCXO Frequency Synchronization
An external VCXO can be used to provide a clock
to the transmission components. This clock is con-
trolled by the main clock distribution (Clock A or
Clock B at 4096kHz). As the clock of the transmis-
sion component is 15360 or 16384kHz,a configur-
able function is necessary.
The VCXO frequency is divided by P (30 or 32) to
provide a common sub-multiple (512kHz) of the
reference frequency CLOCKA or CLOCKB
(4096kHz). The comparison of these two signals
gives an error signal which commands the VCXO.
Two external pins are needed to perform this func-
tion : VCXO-IN and VCXO-OUT (see Figure 32 on
Page 42).
Frame
Clock
SYN1
ADAPTATION
CLOCK
S YN0
To th e inte rnal
MHDLC
FSCV*
FSCGCI
DCLK
STLC5465B
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