STLC5465B STMicroelectronics, STLC5465B Datasheet - Page 15

• Manufacturer Part Number: STLC5465B
• Description: Telecom ICs Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom IC - Variousr

Specifications of STLC5465B

• Operating Supply Voltage: 4.75 V to 5.25 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-160
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

III - FUNCTIONAL DESCRIPTION
III.1 - The Switching Matrix N x 64 KBits/S
III.1.1 - Function Description
The matrix performs a non-blocking switch of 256
time slots from 8 Input Time Division Multiplex
(TDM) at 2 Mbit/s to 8 output Time Division Multi-
plex. A TDM is composed of 32 Time Slots (TS) at
64 kbit/s. The matrix is designed to switch a 64
kbit/s channel (Variable delay mode) or an hyper-
channel of data (Sequence integrity mode). So, it
will both provide minimum throughput switching
delay for voice applications and time slot sequence
integrity for data applications on a per channel
basis.
The requirements of the Sequence Integrity (n*64
kbit/s) mode are the following:
All the time slots of a given input frame must be put
out during a same output frame.
The time slots of an hyperchannel (concatenation
of TS in the same TDM) are not crossed together
at output in different frames.
In variable delay mode, the time slot is put out as
soon as possible. (The delay is two or three time
slots minimum between input and output).
For test facilities, any time slot of an Output TDM
(OTDM) can be internally looped back into the
same Input TDM number (ITDM) at the same time
slot number.
A Pseudo Random Sequence Generator and a
Pseudo Random Sequence Analyzer are imple-
mented in the matrix. They allow the generation a
sequence on a channel or on a hyperchannel, to
analyse it and verify its integrity after several
switching in the matrix or some passing of the
sequence across different boards.
The Frame Signal (FS) synchronises ITDM and
OTDM but a programmable delay or advance can
be introduced separatelyon each ITDM and OTDM
(a half bit time, a bit time or two bit times).
An additional pin (PSS) permits the generation of
a programmable signal composed of 256 bits per
frame at a bit rate of 2048 kbit/s.
An external pin (NDIS) asserts a high impedance
on all the TDM outputs of the matrix when active
(during the initialization of the board for example).
III.1.2 - Architecture of the Matrix
The matrix is essentially composed of buffer data
memories and a connection memory.
The received serial data is first converted to parallel
by a serial to parallelconverterand stored consecu-
tively in a 256 position Buffer Data Memory (see
Figure 2 on Page 16).
To satisfy the Sequence Integrity (n*64 kbit/s) re-
quirements, the data memory is built with an even
memory, an odd memory and an output memory.
Two consecutive frames are stored alternatively in
the odd and even memory. During the time an input
frame is stored, the one previously stored is trans-
ferred into the output memory according to the
connectionmemoryswitching orders. Aframe later,
the output memory is read and data is converted to
serial and transferred to the output TDM.
III.1.3 - Connection Function
Two types of connections are offered :
- unidirectional connection and
- bidirectional connection.
An unidirectionalconnection makes only the switch
of an input time slot through an output one whereas
a bidirectionalconnectionestablishesthe link in the
other direction too. So a double connection can be
achieved by a single command (see Figure 3 on
Page 17).
III.1.4 - Loop Back Function
Any time slot of an Output TDM can be internally
looped back on the time slot which has the same
TDM number and the same TS number
In the case of a bidirectional connection, only the
one specified by the microprocessor is concerned
by the loop back (see Figure 4 on Page 17).
(OTDMi, TSj) ----> (ITDMi, TSj).
STLC5465B
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