AD9923BBCZ Analog Devices Inc, AD9923BBCZ Datasheet
AD9923BBCZ
Specifications of AD9923BBCZ
Available stocks
Related parts for AD9923BBCZ
AD9923BBCZ Summary of contents
Page 1
FEATURES Integrated 15-channel V-driver 12-bit 36 MHz analog-to-digital converter (ADC) Similar register map to AD9994 5-field, 10-phase vertical clock support Complete on-chip timing generator Precision Timing core with <600 ps resolution Correlated double sampler (CDS ...
Page 2
AD9923 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Specifications..................................................................................... 3 Digital Specifications ................................................................... 4 H-Driver Specifications ............................................................... 4 Vertical Driver Specifications ..................................................... 4 Analog Specifications................................................................... 5 Timing Specifications .................................................................. 6 ...
Page 3
SPECIFICATIONS Table 1. Parameter TEMPERATURE RANGE Operating Storage AFETG POWER SUPPLY VOLTAGES AVDD (AFE Analog Supply) TCVDD (Timing Core Analog Supply) RGVDD (RG Driver) HVDD (HL Drivers) DRVDD (Data Output Drivers) DVDD (Digital) V-DRIVER POWER SUPPLY VOLTAGES ...
Page 4
AD9923 DIGITAL SPECIFICATIONS DRVDD = MIN Table 2. Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance ...
Page 5
Parameter Rise Time, VLL to VMM Rise Time, VMM to VH Fall Time VLL Fall Time VMM Fall Time, VMM to VLL Output Currents @ −7. −0. +0. +14.75 V ...
Page 6
AD9923 Parameter ANALOG-TO-DIGITAL CONVERTER (ADC) Resolution Differential Nonlinearity (DNL) No Missing Codes Full-Scale Input Voltage VOLTAGE REFERENCE Reference Top Voltage (REFT) Reference Bottom Voltage (REFB) SYSTEM PERFORMANCE Gain Accuracy Low Gain (VGA Code 15) Maximum Gain (VGA Code 1023) Peak ...
Page 7
ABSOLUTE MAXIMUM RATINGS Table 7. Parameter To AVDD AVSS TCVDD TCVSS HVDD HVSS RGVDD RGVSS DVDD DVSS DRVDD DRVSS VDD1 VSS1 VDD2 VSS2 VH1 VL1 VH2 VL1 VH1 VSS1 VH2 VSS1 VL1 VSS1 VL2 VSS1 VM1 VSS1 VM2 VSS1 VLL ...
Page 8
AD9923 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 8. Pin Function Descriptions Pin No. A7 A1, A4, B2, B3, B4, B5, B6 K8, L7 D10 B10 A10 L10 K10 ...
Page 9
Pin No F11 E11 D11 C11 B11 C10 G10 F10 C6 C7 G11 H11 ...
Page 10
AD9923 TYPICAL PERFORMANCE CHARACTERISTICS 500 450 3.3V 400 350 300 250 200 150 100 FREQUENCY (MHz) Figure 5. Power vs. Sample Rate 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 0 500 1000 1500 2000 2500 CODE ...
Page 11
EQUIVALENT CIRCUITS AVDD R AVSS Figure 9. CCDIN, CCDGND DVDD DATA THREE-STATE DVSS Figure 10. Digital Data Outputs DVDD 330Ω DVSS Figure 11. Digital Inputs RG, HL, H1–H4 THREE-STATE AVSS DRVDD DOUT DRVSS Rev Page ...
Page 12
AD9923 TERMINOLOGY Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore, every code must have a finite width. No missing codes guaranteed to 12-bit resolution ...
Page 13
THEORY OF OPERATION Figure 14 shows the typical system block diagram for the AD9923 in master mode. The CCD output is processed by the AD9923 AFE circuitry, which consists of a CDS, VGA, black level clamp, and ADC. The digitized ...
Page 14
AD9923 PRECISION TIMING HIGH SPEED TIMING GENERATION The AD9923 generates high speed timing signals using the flexible Precision Timing core. This core is the foundation for generating the timing used for both the CCD and the AFE. It consists of ...
Page 15
Table 10. Precision Timing Edge Locations Quadrant Edge Location (Decimal III POSITION P[0] CLI t CLIDLY 1 PIXEL PERIOD NOTES THE PIXEL CLOCK PERIOD IS ...
Page 16
AD9923 CCD SIGNAL RG HL/H1/H3 H2/H4 NOTES 1. USING THE SAME TOGGLE POSITIONS FOR H1 AND H3 GENERATES STANDARD 2-PHASE H-CLOCKING. POSITION P[0] PIXEL PERIOD RGr[0] RG Hr[0] HL/H1/H3 H2/H4 CCD SIGNAL NOTES 1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE ...
Page 17
P[0] PIXEL PERIOD DCLK t OD DOUT NOTES 1. DATA OUTPUT (DOUT) AND DCLK PHASE ARE ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD. 2. WITHIN 1 CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 48 DIFFERENT LOCATIONS ...
Page 18
AD9923 HORIZONTAL CLAMPING AND BLANKING The AD9923 horizontal clamping and blanking pulses are fully programmable to suit a variety of applications. Individual controls are provided for CLPOB, PBLK, and HBLK during different regions of each field. This allows dark pixel ...
Page 19
VD NO CLPOB SIGNAL FOR LINES CLPOB CLPMASKSTART1 = 6 NO CLPOB SIGNAL VD FOR LINES PBLK PBLKMASKSTART1 = 6 NO CLPOB SIGNAL FOR LINE 600 ...
Page 20
AD9923 Individual HBLK Patterns The HBLK programmable timing shown in Figure 26 is similar to CLPOB and PBLK; however, there is no start polarity control. Only the toggle positions are used to designate the start and end positions of the ...
Page 21
HD HBL K HL/H1/H3 THE POLARITY OF HL/H1/H3 DURING BLANKING ARE INDEPENDENTLY PROGRAMMABLE (H2/H4 IS OPPOSITE POLARITY OF H1/H3) H1/H3 H2/H4 HBLKTOGE2 HBLKTOGE1 HBLK HL/H1/H3 H2/H4 SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS (HBLKALT = 0) Figure ...
Page 22
AD9923 Generating HBLK Line Alternation The AD9923 can alternate different HBLK toggle positions on odd and even lines. This feature can be used in conjunction with V-pattern odd/even alternation its own. When 1 is written to the HBLKALT ...
Page 23
ODD LINE HD HBLKTOGO2 HBLKTOGO1 HBLKTOGO3 HBLK HL/H1/H3 H2/H4 Figure 31. HBLK Odd/Even Alternation Using HBLKALT = 3 HBLKTOGE2 HBLKSTART HBLKTOGE1 HBLKTOGE3 HBLK HBLKLEN HBLKREP = 3 HL/H1/H3 H2/H4 HBLKREP NUMBER 1 H-BLANK REPEATING PATTERN IS CREATED USING HBLKLEN AND ...
Page 24
AD9923 Increasing H-Clock Width During HBLK The AD9923 allows the pulse width to be increased during the HBLK interval. The H-clock pulse width can increase by reducing the H-clock frequency (see Table 13). The HBLKWIDTH register (Register ...
Page 25
VERTICAL TIMING GENERATION The AD9923 provides a very flexible solution for generating vertical CCD timing; it can support multiple CCDs and different system architectures. The 13-phase vertical transfer clocks, XV1 to XV13, are used to shift lines of pixels into ...
Page 26
AD9923 Vertical Pattern (VPAT) Groups A vertical pattern (VPAT) group defines the individual pulse pattern for each XV1 to XV13 output signal. Table 14 summarizes the registers that are available for generating each VPAT group. The first, second, third, fourth, ...
Page 27
Vertical Sequences (VSEQ) A vertical sequence (VSEQ) is created by selecting one of the V-pattern groups and adding repeats, a start position, and horizontal clamping and blanking information. Each VSEQ is programmed using the registers shown in Table 15. Figure ...
Page 28
AD9923 Table 15. V-Sequence Registers (See Table 11 and Table 12 for CLPOB, PBLK, and HBLK Registers.) Length Register (Bits) Range HOLD 1 On/off VMASK mask mode HDLEN 8191 pixels XV1POL to 1 ...
Page 29
Group A/Group B Selection The AD9923 has the flexibility to use two V-pattern groups in a vertical sequence. In general, all vertical outputs use the same V-pattern group during a sequence, but some outputs can be assigned to a different ...
Page 30
AD9923 Generating Line Alternation for V-Sequences and HBLK During low resolution readout, some CCDs require a different number of vertical clocks on alternate lines. The AD9923 can support such CCDs by using different VREP registers. This allows a different number ...
Page 31
Masking Using Freeze/Resume Registers As shown in Figure 42 and Figure 43, the FREEZE/RESUME registers are used to temporarily mask the XV outputs. The pixel locations to start (FREEZE) and end (RESUME) the masking create an area in which the ...
Page 32
AD9923 Hold Area Using FREEZE/RESUME Registers The FREEZE/RESUME registers can also be used to create a hold area, in which the XV outputs are temporarily held and then later resume at the point where they were held. As shown in ...
Page 33
Complete Field: Combining V-Sequences After the V-sequences are created, they are combined to create different readout fields. A field consists seven regions. Within each region, a different V-sequence can be selected. Figure 46 shows how the sequence ...
Page 34
AD9923 SCP 0 SCP 1 VD REGION 0 REGION 1 HD XV1 TO XV13 VSEQSEL0 VSEQSEL1 VSG FIELD SETTINGS: 1. SEQUENCE CHANGE POSITIONS (SCP1 TO SCP6) DEFINE EACH OF THE NINE AVAILABLE REGIONS IN THE FIELD. 2. VSEQSEL0 TO VSEQSEL8 ...
Page 35
HD VSG XV1 XV2 XV13 VD HD LINE 0 XV1 TO XV13 REGION 0 Figure 48 shows an example of sweep mode operation. The number of required vertical pulses depends on the vertical resolution of the CCD. The XV1 to ...
Page 36
AD9923 Pixel 2 and Pixel 9 within a single HD line. However, in multiplier mode the toggle positions are multiplied by VLEN = 4; therefore, the first toggle occurs at pixel count = 8, Table 18. Multiplier Mode Register Parameters ...
Page 37
Vertical Sensor Gate (Shift Gate) Patterns In an interline CCD, the vertical sensor gates (VSG) are used to transfer the pixel charges from the light sensitive image area into the light shielded vertical registers. From the light shielded vertical registers, ...
Page 38
AD9923 MODE Register The MODE register is a single register that selects the field timing of the AD9923. Typically, all field, V-sequence, and V-pattern group information is programmed into the AD9923 at startup. During operation, the MODE register allows the ...
Page 39
VERTICAL TIMING EXAMPLE To better understand how the AD9923 vertical timing generation is used, consider the example CCD timing chart in Figure 52. It illustrates a CCD using a general 3-field readout technique. As described in the Complete Field: Combining ...
Page 40
AD9923 Figure 52. CCD Timing Example—Dividing Each Field into Regions Rev Page 05586-051 N N– N–1 N– N–2 N– ...
Page 41
VERTICAL DRIVER SIGNAL CONFIGURATION As shown in Figure 53, XV1 to XV13, VSG1 to VSG8, and XSUBCK are outputs from the internal AD9923 timing generator, and V1 to V13 and SUBCK are the resulting outputs from the AD9923 vertical driver. ...
Page 42
AD9923 Table 21. V1 Output Polarity Vertical Driver Input XV1 VSG1 Table 22. V3 Output Polarity Vertical Driver Input XV3 VSG3 Table 23. V5A ...
Page 43
Table 34. V10 Output Polarity Vertical Driver Input V10 Output XV10 Table 35. V13 Output Polarity Vertical Driver Input V13 Output XV13 XV1 VSG1 XV11 VSG2 VH V11 ...
Page 44
AD9923 XV12 VSG4 VH V12 VM VL XV5 VSG5 VH V5A VM VL XV5 VSG6 VH V5B VM VL XV7 VSG7 VH V7A VM VL Figure 57. XV12, VSG4, and V12 Output Polarities Figure 58. XV5, VSG5, and V5A Output ...
Page 45
XV7 VSG8 VH V7B VM VL XV2, XV4, XV6, XV8 XV9, XV10, XV13 VM V2, V4, V6, V8 V9, V10 Figure 62. XV2, XV4, XV6, XV8, XV9, XV10, XV13 and V2, V4, V6, V8, V9, V10, V13 Output ...
Page 46
AD9923 SHUTTER TIMING CONTROL The CCD image exposure time is controlled by the substrate clock signal (SUBCK), which pulses the CCD substrate to clear out accumulated charge. The AD9923 supports three types of electronic shuttering: normal, high precision, and low ...
Page 47
VD HD VSG SUBCK SUBCK PROGRAMMABLE SETTINGS: 1. PULSE POLARITY USING THE SUBCKPOL REGISTER. 2. NUMBER OF PULSES WITHIN THE FIELD USING THE SUBCKNUM REGISTER (SUBNUM = 3 IN THE ABOVE EXAMPLE). 3. PIXEL LOCATION OF PULSE WITHIN THE LINE ...
Page 48
AD9923 SUBCK Suppression Normally, the SUBCK begins pulsing on the line following the sensor gate line (VSG). Some CCDs require suppressing the SUBCK pulse for one or more lines following the VSG line. The SUBCKSUPPRESS register enables such suppression. Readout ...
Page 49
Table 38. SUBCK and TRIGGER Register Parameters Length Register (Bits) Range TRIGGER 8 On/off for eight signals READOUTNUM fields EXPOSURENUM 4095 fields VDHDOFF 1 On/off 1 SUBCKPOL 1 High/low 1 SUBCK1TOG1 12 0 ...
Page 50
AD9923 Automatic Trigger Generally, SHUT signals are triggered along with an exposure or readout operation, using the TRIGGER register. The SHUT_ON and SHUT_OFF positions are fully programmable to anywhere within the exposure period, using the field (SHUT_ON_FD/SHUT_OFF_FD), line (SHUT_ON_LN/SHUT_OFF_LN), and ...
Page 51
TRIGGER VSUB VD VSG1 SUBCK 2 VSUB MODE 0 1 VSUB OPERATION: 1. ACTIVE POLARITY IS DEFINED BY VSUBPOL (ABOVE EXAMPLE IS VSUB ACTIVE HIGH POSITION IS PROGRAMMABLE, MODE 0 TURNS ON AT THE START OF EXPOSURE, MODE ...
Page 52
AD9923 Table 39. VSUB0 to VSUB1 and SHUT0 to SHUT3 Register Parameters Length Register (Bits) Range VSUB_CTRL MSHUT_CTRL STROBE_CTRL TESTO_CTRL VSUB0_MUX 1 High/low VSUB1_MUX ...
Page 53
Length Register (Bits) Range SHUT_ON 1 On/off SHUTPOL 1 High/low SHUT_MAN 1 Enable/disable SHUT_ON_FD 4095 field location SHUT_ON_LN 4095 line location SHUT_ON_PX 8191 pixel location SHUT_OFF_FD 4095 field ...
Page 54
AD9923 EXAMPLE OF EXPOSURE AND READOUT OF INTERLACED FRAME Figure 70. Example of Exposure and Still Image Readout Using Shutter Signals and Mode Register 05586-069 Rev Page ...
Page 55
Explanation of Figure 70 The numbers in the Explanation of Figure 70 section correspond to the numbers embedded in Figure 70. 1. Write to the READOUTNUM register (Address 0x62) to specify the number of fields to suppress SUBCK during readout ...
Page 56
AD9923 FG_TRIG OPERATION The AD9923 contains one additional signal that can be used in conjunction with shutter operation or general system operation. The FG_TRIG signal is an internally generated pulse that can be output on the SYNC pins for shutter ...
Page 57
DC RESTORE 1.5V 0.1μF CCDIN SHP CLI GENERATION ANALOG FRONT END DESCRIPTION/OPERATION The AD9923 signal processing chain is shown in Figure 72. Each step is essential to achieve a high quality image from the raw CCD pixel data. DC Restore ...
Page 58
AD9923 Optical Black Clamp The optical black clamp loop is used to remove residual offsets in the signal chain and to track low frequency variations in the CCD black level. During the optical black (shielded) pixel interval on each line, ...
Page 59
Recommended Power-Up Sequence for Master Mode When the AD9923 is powered up, the following sequence is recommended (see Figure 74): 1. Turn on the power supplies for the AD9923, and start the master clock, CLI. 2. Reset the internal AD9923 ...
Page 60
AD9923 Table 41. Power-Up Register Write Sequence Register Address SW_RST 0x10 STANDBY3POL 0xE2 0x20 to 0xFFF STANDBY 0x00 TEST3 0xEA OSC_RST 0x16 TGCORE_RSTB 0x15 MASTER 0x20 OUTCONTROL 0x11 SYNCPOL 0x13 Generating Software Sync Without External Sync Signal If an external ...
Page 61
Power-Up and Synchronization in Slave Mode The power-up procedure for slave mode operation is the same as the procedure described for master mode operation, with two exceptions: • Eliminate Step 8. Do not configure the part for master mode timing. ...
Page 62
AD9923 VD HD H-COUNTER N-28 N-27 N-26 N-25 N-24 (PIXEL COUNTER) NOTE TOGGLE POSITIONS CANNOT BE PROGRAMMED WITHIN 28 PIXELS OF PIXEL 0 LOCATION H-COUNTER N-33 N-32 N-31 N-30 N-29 N-28 N-27 N-26 (PIXEL COUNTER) NOTE TOGGLE POSITIONS ...
Page 63
STANDBY MODE OPERATION The AD9923 contains three standby modes to optimize the overall power dissipation in various applications. Bits[1:0] of Register 0x00 control the power-down state of the device: STANDBY[1: normal operation (full power) STANDBY[1: ...
Page 64
AD9923 Table 43. Standby Mode Operation—Vertical and Shutter Outputs Output Standby 3 (default) XV1 LO XV2 LO XV3 LO XV4 LO XV5 LO XV6 LO XV7 LO XV8 LO XV9 LO XV10 LO XV11 LO XV12 LO XV13 LO VSG1 ...
Page 65
CIRCUIT LAYOUT INFORMATION The AD9923 typical circuit connections are shown in Figure 81. The PCB layout is critical for achieving good image quality from the AD9923. All supply pins, particularly the pins for the AVDD, TCVDD, RGVDD, and HVDD supplies, ...
Page 66
... L9 NC L11 NC = NOT INTERNALLY CONNECTED 3 DCLK OUTPUT AD9923BBCZ (Not to Scale) 15 Figure 81. AD9923BBCZ Typical Circuit Configuration Rev Page MASTER CLOCK INPUT OPTIONAL CLOCK OSCILLATOR OUTPUT (FOR CRYSTAL APPLICATION) VSUB OUTPUT (TO CCD BIAS CIRCUIT) STROBE CONTROL OUTPUT MECHANICAL SHUTTER CONTROL OUTPUT 0.1μF ...
Page 67
SERIAL INTERFACE TIMING All of the AD9923 internal registers are accessed through a 3-wire serial interface. Each register consists of a 12-bit address and a 28-bit data-word. Both the address and data-word are written by starting with the LSB. To ...
Page 68
AD9923 LAYOUT OF INTERNAL REGISTERS The AD9923 address space is divided into two register areas, as illustrated in Figure 84. In the first area, Address 0x00 to Address 0x91 contain the registers for the AFE, miscellaneous functions, VD/HD parameters, timing ...
Page 69
ADDR 0x400 3 V-PATTERN GROUPS (40 × 120 REGISTERS) ADDR 0x478 4 V-SEQUENCES (20 × REGISTERS) ADDR 0x4B4 2 FIELDS (12 × REGISTERS) ADDR 0x4CC UNUSED MEMORY MAX 0x7FF Figure 85. Example ...
Page 70
AD9923 COMPLETE REGISTER LISTING When an address contains less than 28 data bits, all remaining bits must be written as 0s. Table 45. AFE Registers Data Default Update Address Bits Value Type 00 [1:0] 3 SCK [2] 1 [3] 0 ...
Page 71
Table 46. Miscellaneous Registers Data Default Update Address Bits Value Type 10 [0] 0 SCK 11 [ [0] 1 SCK [7:1] 0 [9: [0] 0 SCK 14 [0] 0 SCK 15 [0] 0 SCK 16 ...
Page 72
AD9923 Table 48. Timing Core Registers Data Default Update Address Bits Value Type 30 [0] 0 SCK 31 [5:0] 0 SCK [13:8] 20 [16 [5:0] 0 SCK [13:8] 20 [16 [5:0] 0 SCK [13:8] 20 [16] ...
Page 73
Data Default Update Address Bits Value Type [7:4] 1 [11:8] 1 [15:12] 1 [19:16] 1 [23:20 [7:0] 24 SCK [15: [5:0] 0 SCK [7:6] 0 [8] 0 [10:9] 2 [11] 0 Table 49. CLPOB and PBLK ...
Page 74
AD9923 Table 50. SG Pattern Registers Data Default Update Address Bits Value Type 50 [ [1] 1 [2] 1 [3] 1 [4] 1 [5] 1 [ [12:0] 1FFF VD [25:13] 1FFF 52 [12:0] 1FFF ...
Page 75
Table 51. Shutter Control Registers Data Default Update Address Bits Value Type 60 [2: [5:3] 0 [8:6] 0 [11: [7: Name Description VSUB_CTRL Selects which internal signal is used for the VSUB output pin. ...
Page 76
AD9923 Data Default Update Address Bits Value Type 62 [2: [11: [12] 64 [11: [23:12] 65 [1: [ [12:0] 1FFF SG [25:13] 1FFF 68 [12:0] ...
Page 77
Data Default Update Address Bits Value Type 71 [11: [12] 0 [25:13 [ [ [11: [11: [12] 0 [25:13 [11:0] 0 ...
Page 78
AD9923 Data Default Update Address Bits Value Type [12: Table 52. Memory Configuration Registers Data Default Address Bits Value Update 90 [4: [4: Table 53. Memory Configuration Registers Data ...
Page 79
Data Default Address Bits Value Update F1 [3:0] 0 SCK F3 [21:0] 3FE000 SCK Table 54. Mode Register: VD Updated Address Data Bits 12b10_xx_xxxx_xxxx [37:0] (Set A11, A10 = 10) [37:35] [34:30] [29:25] [27:20] [19:15] [14:10] [9:5] [4:0] Name Description ...
Page 80
AD9923 Unused XV-channels must have toggle positions programmed to maximum values. For example, if XV1 to XV8 are used, XV9 to XV12 must have all toggle positions set to maximum values. This prevents unpredictable behavior, because default values are unknown. ...
Page 81
Address Data Bits Default Value 18 [12:0] X [25:13 [12:0] X [25:13 [12:0] X [25:13 [12:0] X [25:13 [12:0] X [25:13 [12:0] X [25:13 [12:0] X [25:13] X ...
Page 82
AD9923 Data Default Update Address Bits Value Type [5] X [6] X [7] X [8] X [9] X [10] X [11] X [12] X [13] X [14] X [15] X [16] X [17] X [18] X [19] X [20] X ...
Page 83
Data Default Update Address Bits Value Type [25:13 [12:0] X SCP [25:13 [12:0] X SCP 25:13 [12:0] X SCP [25:13 [12:0] X SCP [20:13] X [21] X [22] X [23 ...
Page 84
AD9923 Data Default Update Address Bits Value Type 03 [11: [12] X [24:13 [11: [24:13] X [24:13 [11: [12] X [24:13 [11: [12] X [24:13] X ...
Page 85
... OUTLINE DIMENSIONS *1.40 1.31 1.16 ORDERING GUIDE Model Temperature Range AD9923BBCZ −25° 85°C AD9923BBCZRL −25° 85°C 8.00 BSC BALL CORNER 6.50 TOP VIEW BSC SQ 0.65 BSC DETAIL A 0.25 MIN 0.45 0.40 0.35 BALL DIAMETER * COMPLIANT TO JEDEC STANDARDS MO-225 WITH THE EXCEPTION TO PACKAGE HEIGHT. ...
Page 86
AD9923 Rev Page ...
Page 87
NOTES Rev Page AD9923 ...
Page 88
AD9923 NOTES ©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05586-0-7/05(0) T Rev Page ...