AD9923BBCZ Analog Devices Inc, AD9923BBCZ Datasheet - Page 39

• Manufacturer Part Number: AD9923BBCZ
• Manufacturer: Analog Devices Inc

Specifications of AD9923BBCZ

• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 36MSPS
• Input Voltage Range: 0.7V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 105
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Compliant

VERTICAL TIMING EXAMPLE
To better understand how the AD9923 vertical timing
generation is used, consider the example CCD timing chart in
Figure 52. It illustrates a CCD using a general 3-field readout
technique. As described in the Complete Field: Combining V-
Sequences section, each readout field should be divided into
separate regions to perform each step of the readout. The
sequence change position (SCP) registers determine the line
boundaries for each region. Then, the VSEQSEL registers assign
a V-sequence to each region. Each V-sequence contains specific
timing information required for each region: XV1 to XV6
pulses (using VPAT groups), HBLK/CLPOB timing, and VSG
patterns for the SG active lines.
The example shown in Figure 52 requires four regions, labeled
Region 0, Region 1, Region 2, and Region 3, for each of the
three fields. Because the AD9923 allows many individual fields
to be programmed, Field 0, Field 1, and Field 2 can be created to
meet the requirements of this timing example. In this example,
the four regions for each field are very similar, but the individual
registers for each field allow flexibility to accommodate more
complex timing requirements.
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Region 0 is a high speed vertical shift region. Sweep mode can
be used to generate this timing operation, with the desired
number of high speed vertical pulses needed to clear any charge
from the vertical registers of the CCD.
Region 1 consists of two lines and uses standard, single-line,
vertical-shift timing. The timing of this region is the same as the
timing of Region 3.
Region 2 is the sensor gate line, where the VSG pulses transfer
the image into the vertical CCD registers. This region might
require use of the second V-pattern group for the SG active line.
Region 3 also uses the standard, single line, vertical shift timing,
the same timing used in Region 1. In summary, four regions are
required in each of the three fields.
The timing for Region 1 and Region 3 is essentially the same,
reducing the complexity of the register programming. Other
registers, such as the MODE register, shutter control registers
(that is, TRIGGER, and the registers to control the SUBCK,
VSUB, MSHUT, and STROBE outputs), and the AFE gain
registers, VGAGAIN and CDSGAIN, must be used during the
readout operation. These registers are explained in the MODE
Register and Variable Gain Amplifier sections.
AD9923