AD9923BBCZ Analog Devices Inc, AD9923BBCZ Datasheet - Page 37

• Manufacturer Part Number: AD9923BBCZ
• Manufacturer: Analog Devices Inc

Specifications of AD9923BBCZ

• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 36MSPS
• Input Voltage Range: 0.7V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 105
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Compliant

Vertical Sensor Gate (Shift Gate) Patterns
In an interline CCD, the vertical sensor gates (VSG) are used to
transfer the pixel charges from the light sensitive image area
into the light shielded vertical registers. From the light shielded
vertical registers, the image is then read line-by-line using the
XV1 to XV13 vertical transfer pulses in conjunction with the
high speed horizontal clocks.
Table 19 summarizes the VSG pattern registers. The AD9923
has eight VSG outputs, VSG1 to VSG8. Each output can be
assigned to one of eight programmed patterns by using the
SGPATSEL register. Each pattern is generated in a similar
manner as the V-pattern groups, with a programmable start
polarity (SGPOL), first toggle position (SGTOG1), and second
toggle position (SGTOG2). The active line where the VSG1 to
VSG8 pulses occur is programmable using the SGACTLINE1
Table 19. VSG Pattern Registers
Register
SGPOL
SGTOG1
SGTOG2
SGMASK_BYP
SGMASK_BYP_EN
1
See field registers in Table 16.
VSG PATTERNS
Length
(Bits)
1
13
13
8
1
VD
HD
PROGRAMMABLE SETTINGS FOR EACH PATTERN:
1. START POLARITY OF PULSE.
2. FIRST TOGGLE POSITION.
3. SECOND TOGGLE POSITION.
4. ACTIVE LINE FOR VSG PULSES WITHIN THE FIELD (PROGRAMMABLE IN THE FIELD REGISTER, NOT FOR EACH PATTERN).
Range
High/low
0 to 8191 pixel
location
0 to 8191 pixel
location
High/low for
each VSG
0 or 1
1
Figure 50. Vertical Sensor Gate Pulse Placement
Description
Sensor-gate starting polarity for SG patterns 0 to 7
First toggle position for SG patterns 0 to 7
Second toggle position for SG patterns 0 to 7
SGMASK Bypass. This register overrides the SGMASK values in each Field register. One
bit for each output, where Bit[0] is for VSG1 output and Bit[7] is for VSG8 output.
1: Enables SGMASK bypass
0 = active.
1 = mask output.
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and SGACTLINE2 registers. Additionally, any of the VSG1 to
VSG8 pulses can be individually disabled using the SGMASK
register. The individual masking allows all SG patterns to be
preprogrammed, and the appropriate pulses for each field can
be enabled separately. For maximum flexibility, the SGPATSEL,
SGMASK, and SGACTLINE registers are separately programmable
for each field. More detail is given in the Complete Field:
Combining V-Sequences section.
Additionally, there is the SGMASK_BYP register (Address 0x59),
which overrides SG masking in the field registers. The
SGMASK_BYP register allows sensor gate masking to be
changed without modifying the field register values. The
SGMASK_BYP register is SCK updated; therefore, the new SG-
masking values update immediately.
4
1
2
3
AD9923