AD9923BBCZ Analog Devices Inc, AD9923BBCZ Datasheet - Page 63

• Manufacturer Part Number: AD9923BBCZ
• Manufacturer: Analog Devices Inc

Specifications of AD9923BBCZ

• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 36MSPS
• Input Voltage Range: 0.7V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 105
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Compliant

STANDBY MODE OPERATION
The AD9923 contains three standby modes to optimize the
overall power dissipation in various applications. Bits[1:0] of
Register 0x00 control the power-down state of the device:
Table 42 and Table 43 summarize the operation of each power-
down mode. Note that when OUTCONTROL = LO, it takes
priority over the Standby 1 and Standby 2 modes in determining
the digital output states, but Standby 3 mode takes priority over
OUTCONTROL. Standby 3 has the lowest power consumption,
and can shut down the crystal oscillator circuit between CLI
Table 42. Standby Mode Operation
I/O Block
AFE
Timing Core
CLO Oscillator
CLO
HL
H1
H2
H3
H4
RG
VD
HD
DCLK
DOUT
1
2
3
4
To exit Standby 3, write 00 to STANDBY (Bits[1:0], Address 0x00), then reset the timing core after 500 μs to guarantee proper settling of the oscillator.
Standby 3 mode takes priority over OUTCONTROL for determining the output polarities.
These polarities assume OUTCONTROL = HI, because OUTCONTROL = LO takes priority over Standby 1 and Standby 2.
Standby 1 and Standby 2 set H and RG drive strength to their minimum values (4.3 mA).
STANDBY[1:0] = 00 = normal operation (full power)
STANDBY[1:0] = 01 = Standby 1 mode
STANDBY[1:0] = 2 = Standby 2 mode
STANDBY[1:0] = 3 = Standby 3 mode (lowest power)
Standby 3 (default)
Off
Off
HI
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
LO
LO
LO
LO
Off
1, 2
OUTCONTROL = LO
No change
No change
No change
Running
LO
LO
HI
LO
HI
LO
VDHDPOL value
VDHDPOL value
Running
LO
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and CLO. If CLI and CLO are being used with a crystal to
generate the master clock, this circuit is powered down and
there is no clock signal. When returning the device from
Standby 3 mode to normal operation, reset the timing core at
least 500 μs after writing to the OPRMODE register. This allows
sufficient time for the crystal circuit to settle. The vertical and
shutter outputs can be programmed to hold a specific value
during the Standby 3 mode using Register 0xE2, as detailed in
Table 43. The vertical outputs can be programmed to hold a
specific value when OUTCONTROL = LO, or when in Standby 1
or Standby 2 mode, by using Register 0xF3. Please see the
endnote references (Endnote 2 to Endnote 4) following Table 43
for the mapping of the bits in these registers to the various
vertical and shutter outputs when the device is in one of the
three standby modes, or when OUTCONTROL = LO. This
feature is useful during power-up if different polarities are
required by the V-driver and CCD to prevent damage.
Standby 2
Off
Off
On
Running
LO (4.3 mA)
LO (4.3 mA)
HI (4.3 mA)
LO (4.3 mA)
HI (4.3 mA)
LO (4.3 mA)
VDHDPOL value
VDHDPOL value
LO
LO
3, 4
Standby 1
Running
LO (4.3 mA)
Running
Running
LO
Only REFT, REFB on
On
On
LO (4.3 mA)
HI (4.3 mA)
LO (4.3 mA)
HI (4.3 mA)
LO (4.3 mA)
Running
3, 4
AD9923