AD9923BBCZ Analog Devices Inc, AD9923BBCZ Datasheet - Page 35

• Manufacturer Part Number: AD9923BBCZ
• Manufacturer: Analog Devices Inc

Specifications of AD9923BBCZ

• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 36MSPS
• Input Voltage Range: 0.7V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 105
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Compliant

Figure 48 shows an example of sweep mode operation. The
number of required vertical pulses depends on the vertical
resolution of the CCD. The XV1 to XV13 output signals are
generated using the V-pattern registers (shown in Table 14).
A single pulse is created using the polarity and toggle position
registers. The number of repetitions is then programmed to
match the number of vertical shifts required by the CCD.
Repetitions are programmed in the V-sequence registers using
the VREP registers. This produces a pulse train of the appropriate
length. Normally, the pulse train is truncated at the end of the
HD line length, but with sweep mode enabled, the HD
boundaries are ignored. In Figure 48, the sweep region occupies
23 HD lines. After the sweep mode region is complete, normal
sequence operation resumes in the next region. When using
sweep mode, set the region boundaries, using the sequence
change position registers, to the appropriate lines to prevent the
sweep operation from overlapping with the next V-sequence.
Multiplier Mode
To generate very wide vertical timing pulses, a vertical region
can be configured into a multiplier region. This mode uses the
V-pattern registers in a slightly different manner. Multiplier mode
can be used to support unusual CCD timing requirements, such
as vertical pulses that are wider than the 13-bit V-pattern toggle
position counter.
XV1 TO XV13
XV13
VSG
XV1
XV2
HD
VD
HD
LINE 0
REGION 0
LINE 1
Figure 47. Example of Second VPAT Group During Sensor Gate Line
Figure 48. Example of Sweep Region for High Speed Vertical Shift
SCP 1
LINE 2
START POSITION FOR SECOND VPAT GROUP
USES VSTARTSECOND REGISTER
Rev. 0 | Page 35 of 88
REGION 1: SWEEP REGION
The start polarity and toggle positions are used in the same
manner as the standard VPAT group programming, but the
VLEN register is used differently. Instead of using the pixel
counter (HD counter) to specify the toggle position locations
(XVTOG1, XVTOG2, XVTOG3, XVTOG4, XVTOG5, and
XVTOG6) of the VPAT group, the VLEN value is multiplied by
the XVTOG value to allow very long pulses to be generated. To
calculate the exact toggle position, counted in pixels after the
start position, use the following equation:
Because the XVTOG value is multiplied by VLEN value, the
resolution of the toggle position placement is reduced.
If VLEN = 4, the toggle position accuracy is reduced to 4-pixel
steps, instead of single pixel steps. Table 18 summarizes how the
VPAT group registers are used in multiplier mode operation. In
multiplier mode, the VREP registers should be programmed to
the value of the highest toggle position.
The example shown in Figure 49 illustrates this operation. The
first toggle position is 2, and the second toggle position is 9. In
nonmultiplier mode, this causes the V-sequence to toggle at
Multiplier
SECOND VPAT GROUP
Mode
Toggle
Position
LINE 24
=
SCP 2
XVTOG
LINE 25
REGION 2
×
VLEN
AD9923