AD9923BBCZ Analog Devices Inc, AD9923BBCZ Datasheet - Page 6

• Manufacturer Part Number: AD9923BBCZ
• Manufacturer: Analog Devices Inc

Specifications of AD9923BBCZ

• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 36MSPS
• Input Voltage Range: 0.7V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 105
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Compliant

AD9923
Parameter
ANALOG-TO-DIGITAL CONVERTER (ADC)
VOLTAGE REFERENCE
SYSTEM PERFORMANCE
1
TIMING SPECIFICATIONS
C
Table 6.
Parameter
MASTER CLOCK, CLI
AFE SAMPLE LOCATION
DATA OUTPUTS
SERIAL INTERFACE
1
2
Input signal characteristics are defined as shown in Figure 3.
Parameter is programmable.
Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.
L
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
Resolution
Differential Nonlinearity (DNL)
No Missing Codes
Full-Scale Input Voltage
Reference Top Voltage (REFT)
Reference Bottom Voltage (REFB)
Gain Accuracy
Peak Nonlinearity, 500 mV Input Signal
Total Output Noise
Power Supply Rejection (PSR)
CLI Clock Period
CLI High/Low Pulse Width
Delay from CLI Rising Edge to Internal Pixel Position 0
AFE CLPOB Pulse Width
SHP Sample Edge to SHD Sample Edge
Output Delay from DCLK Rising Edge
Inhibited Area for DOUTPHASE Edge Location
Pipeline Delay from SHP/SHD Sampling to DOUT
= 20 pF, AVDD = DVDD = DRVDD = 3.0 V, f
Low Gain (VGA Code 15)
Maximum Gain (VGA Code 1023)
1
1, 2
1
RESET TRANSIENT
Min
12
−1.0
6.0
42.0
CLI
500mV TYP
= 36 MHz, unless otherwise noted.
OPTICAL BLACK PIXEL
Figure 3. Signal Characteristics
Typ
±0.5
Guaranteed
2.0
2.0
1.0
6.5
42.5
0.1
1.0
50
200mV MAX
Rev. 0 | Page 6 of 88
Symbol
t
t
t
t
f
t
t
t
t
t
CONV
CLIDLY
S1
OD
SCLK
LS
LH
DS
DH
DV
INPUT SIGNAL RANGE
Max
+1.0
7.0
43.0
(0dB CDS GAIN)
1V MAX
Unit
bits
LSB
V
V
V
dB
dB
%
LSB rms
dB
Min
27.8
11.2
2
11.6
36
10
10
10
10
10
SHD
16
Includes entire signal chain
AC-grounded input, 6 dB gain applied
Test Conditions/Comments
Default CDS gain (0 dB)
12 dB gain applied
Measured with step change on supply
Typ
13.9
6
20
13.9
8
Max
16.6
SHD + 11
Unit
ns
ns
ns
pixels
ns
ns
edge location
cycles
MHz
ns
ns
ns
ns
ns