AD9923BBCZ Analog Devices Inc, AD9923BBCZ Datasheet - Page 33

• Manufacturer Part Number: AD9923BBCZ
• Manufacturer: Analog Devices Inc

Specifications of AD9923BBCZ

• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 36MSPS
• Input Voltage Range: 0.7V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 105
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Compliant

Complete Field: Combining V-Sequences
After the V-sequences are created, they are combined to create
different readout fields. A field consists of up to seven regions.
Within each region, a different V-sequence can be selected.
Figure 46 shows how the sequence change position (SCP)
registers designate the line boundary for each region and how
the VSEQSEL registers select the V-sequence for each region.
Registers to control the VSG outputs are also included in the
field registers. Table 16 summarizes the registers used to create
the different fields.
The VSEQSEL registers, one for each region, select which
V-sequences are active during each region. The SWEEP
registers can enable the sweep mode during any region.
The MULTI registers are used to enable the multiplier mode
during any region. The SCP registers create the line boundaries
for each region. The VDLEN register specifies the total number
of lines in the field. The total number of pixels per line
Table 16. Field Registers
Register
VSEQSEL
SWEEP
MULTI
SCP
VDLEN
HDLAST
VSTARTSECOND
VPATSECOND
SGMASK
SGPATSEL
SGACTLINE1
SGACTLINE2
Length
(Bits)
5
1
1
12
12
13
13
5
16
24
12
12
Range
0 to 31 V-sequence
number
High/low
High/low
0 to 4095 line number
0 to 4095 lines
0 to 8191 pixels
0 to 8191 pixels
0 to 31 V-pattern
group number
High/low, each VSG
0 to 7 pattern
number, each VSG
0 to 4095 line number
0 to 4095 line number
Description
Selected V-sequence for each region in the field.
Enables sweep mode for each region when set high.
Enables multiplier mode for each region when set high.
Sequence change position (SCP) for each region.
Total number of lines in each field.
Length in pixels of the last HD line in each field.
Start position of the second V-pattern group applied during VSG line.
Selected V-pattern group for the second pattern applied during VSG line.
Set high to mask each VSG output. Two bits for each VSG output: one for SGLINE1,
and one for SGLINE2.
Selects the VSG pattern number for each VSG output. VSG1[2:0], VSG2[5:3],
VSG3[8:6], VSG4[11:9], VSG5[14:12], VSG6[17:15], VSG7[20:18], VSG8[23:21].
Selects the line in the field where the VSG is active.
Selects a second line in the field to repeat the VSG signals.
[0] Masking for VSG1 on SGLINE1.
[1] Masking for VSG1 on SGLINE2
[2] Masking for VSG2 on SGLINE1.
[3] Masking for VSG2 on SGLINE2.
[15] Masking for VSG8 on SGLINE1.
[16] Masking for VSG8 on SGLINE2.
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(HDLEN) is specified in the V-sequence registers, and the
HDLAST register specifies the number of pixels in the last line
of the field. The VPATSECOND register is used to add a second
V-pattern group to the XV1 to X12 outputs during the sensor
gate (VSG) line.
The SGMASK register is used to enable or disable each VSG
output. There are two bits for each VSG output to enable
separate masking during SGACTLINE1 and SGACTLINE2.
Setting a masking bit high disables, or masks, the output; setting it
low enables the output. The SGPATSEL register assigns one of the
eight SG patterns to each VSG output. Each SG pattern is created
separately using the SG pattern registers. The SGACTLINE1
register specifies which line in the field contains the VSG
outputs. The optional SGACTLINE2 register allows the same
VSG pulses to repeat on a different line, although separate
masking is available for SGACTLINE1 and SGACTLINE2.
AD9923