AD9923BBCZ Analog Devices Inc, AD9923BBCZ Datasheet - Page 59

• Manufacturer Part Number: AD9923BBCZ
• Manufacturer: Analog Devices Inc

Specifications of AD9923BBCZ

• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 36MSPS
• Input Voltage Range: 0.7V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 105
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Compliant

Recommended Power-Up Sequence for Master Mode
When the AD9923 is powered up, the following sequence is
recommended (see Figure 74):
1.
2.
3.
4.
5.
6.
Turn on the power supplies for the AD9923, and start the
master clock, CLI.
Reset the internal AD9923 registers by writing 1 to the
SW_RST register (Address 0x10).
By default, all vertical outputs (XV, VSG, SUBCK) are low.
If necessary, write to the STANDBY3POL Register 0xE2
to set different polarities for the vertical outputs to avoid
damage to the V-driver and the CCD. See Table 43 for
more information on polarities.
Bring the V5V pin high. V5V should be driven with a 3 V
signal through a diode (see Figure 81). V5V must reach a
minimum voltage of 2.3 V before continuing with the
power-up sequence.
VH and VL, the V-driver supplies, can be powered up
after completing Step 3 and Step 4. There are no restrictions
on the order in which VH and VL are powered up.
Load the required registers to configure the required
VPAT group, V-sequence, field timing information, high
speed timing, horizontal timing, and shutter timing
information.
SUPPLIES
(OUTPUT)
(OUTPUT)
OUTPUTS
DIGITAL
WRITES
POWER
(INPUT)
SERIAL
(INPUT)
SYNC
CLI
HD
VD
0V
3V SIGNAL TO DRIVE V5V
(HI-Z BY DEFAULT)
H1/H3, RG, DCLK, XV1 TO XV12, VSG1 TO VSG8, SUBCK, STROBE, MSHUT, VSUB
(HI-Z BY DEFAULT)
DVDD = DRVDD = 3V
HVDD = RGVDD = 3V
TCVDD = AVDD = 3V
VDD = 3V
2
3
4
Figure 74. Recommended Power-Up Sequence and Synchronization, Master Mode
5
6
VL SUPPLY FOR V-DRIVER
VH SUPPLY FOR V-DRIVER
Rev. 0 | Page 59 of 88
7
8
7.
8.
9.
10.
11.
9
To place the part into normal power operation, write 0x04
to the AFE STANDBY register (Bits[1:0], Address 0x00).
If the CLO output is being used to drive a crystal, also
power up the CLO oscillator by writing 1 to Register 0x16.
By default, the internal timing core is held in a reset state
with TGCORE_RSTB register = 0. Write 1 to the
TGCORE_RSTB register (Address 0x15) to start the
internal timing core operation. If a 2× clock is used for the
CLI input, set the CLIDIVIDE register (Address 0x30) to
1 before resetting the timing core.
Configure the AD9923 for master mode timing by writing
1 to the MASTER register (Address 0x20).
Write 1 to the OUTCONTROL register (Address 0x11).
This allows the outputs to become active after the next
SYNC rising edge.
Generate a SYNC event. If SYNC is high at power-up,
bring SYNC input low for a minimum of 100 ns. Then,
bring SYNC high. This causes the internal counters to
reset and starts a VD/HD operation. The first VD/HD
edge allows VD register updates to occur, including
OUTCONTROL to enable all outputs. If an external
SYNC pulse is not available, an internal SYNC pulse can
be generated by writing to the SYNCPOL register, as
described in the Generating Software Sync Without
External Sync Signal section.
10
t
SYNC
11
1H
FIRST FIELD
CLOCKS ACTIVE WHEN OUTCONTROL
REGISTER IS UPDATED AT VD/HD EDGE.
1V
AD9923