AD9923BBCZ Analog Devices Inc, AD9923BBCZ Datasheet - Page 61

• Manufacturer Part Number: AD9923BBCZ
• Manufacturer: Analog Devices Inc

Specifications of AD9923BBCZ

• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 36MSPS
• Input Voltage Range: 0.7V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 105
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Compliant

Power-Up and Synchronization in Slave Mode
The power-up procedure for slave mode operation is the same
as the procedure described for master mode operation, with
two exceptions:
•
•
Eliminate Step 8. Do not configure the part for master
mode timing.
No sync pulse is required in slave mode. Substitute Step 10
with starting the external VD and HD signals. This
synchronizes the part, allows the register updates, and
starts the timing operation.
(PIXELCOUNTER)
NOTES
1. INTERNAL HD FALLING EDGE IS LATCHED BY CLI RISING EDGE, THEN LATCHED AGAIN BY SHD INTERNAL FALLING EDGE.
2. INTERNAL H-COUNTER IS ALWAYS RESET 32.5 CLOCK CYCLES AFTER THE INTERNAL HD FALLING EDGE.
3. DEPENDING ON THE VALUE OF SHDLOC, H-COUNTER RESET CAN OCCUR 33 OR 34 CLI CLOCK EDGES AFTER THE EXTERNAL HD FALLING EDGE.
4. SHDLOC = 0 IS SHOWN IN ABOVE EXAMPLE. IN THIS CASE, THE H-COUNTER RESET OCCURS 34 CLI RISING EDGES AFTER HD FALLING EDGE.
H-COUNTER
INTERNAL
INTERNAL
SHD
CLI
VD
HD
HD
X
X
X
3ns MIN
X
3ns MIN
X
X
Figure 76. External VD/HD and Internal H-Counter Synchronization, Slave Mode
X
X
t
CLIDLY
X
X
X
X
X
X
Rev. 0 | Page 61 of 88
X
X
X
32.5 CYCLES
X
X
•
When the AD9923 is used in slave mode, the VD/HD inputs
synchronize the internal counters. After a falling edge of VD,
there is a latency of 34 master clock edges (CLI) after the falling
edge of HD until the internal H-counter is reset. The reset
operation is shown in Figure 76.
Note: If SHDLOC is set so that the 3 ns minimum delay
between the rising edge of SLI and the falling edge of the
internal SHD signal is NOT met, the internal H-counter can
reset after only 33 master clock edges (CLI).
X
X
Note that DCLK will not begin to transition until Step 7
is complete.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
H-COUNTER
RESET
1
AD9923
2