LSI53CF92A LSI, LSI53CF92A Datasheet - Page 130

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

Table 6.13
1. ALE must pulse to capture a new register address.
2. t
3. IF DMA is active, the FIFO register must not be accessed.
4. If RD/ is held LOW, the time from CS/ LOW to stable data is t
5. t
6. If WR/ is held LOW, data setup to CS/ HIGH is t
7. t
6-14
Symbol
HIGH is t
the FIFO Flags register.
10
5
17
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
must also be satisfied.
must also be satisfied.
minimum is (2 *3 t
Parameter
Address setup to ALE LOW
Address hold from ALE LOW
ALE pulse width
ALE LOW to CS/ LOW
CS/ LOW to data valid
CS/ HIGH to ALE HIGH
CS/ setup to RD/ LOW
RD/ pulse width
RD/ HIGH to CS/ HIGH
RD/ LOW to data valid
RD/ HIGH to data bus disable
CS/ setup to WR/ LOW
WR/ pulse width
WR/ HIGH to CS/ HIGH
Data setup to WR/ HIGH
Data hold from WR/ HIGH
WR/ HIGH to ALE HIGH
CS/ or WR/ HIGH to
CS/ or WR/ HIGH
11
Register Interface, Multiplexed PAD Bus
.
Table 6.13
Electrical Specifications
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
CP
+ 5) for successive FIFO reads or a FIFO write/read followed by a read of
lists the Register Interface, Multiplexed PAD bus.
t
CP
3 t
Min
10
10
20
10
30
30
15
–
0
0
0
–
2
0
0
4
CP
15
+5
and data hold from CS/ HIGH is t
t
CP
Max
5
30
30
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
and the data release time from CS/
+30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
16
minimum.
Notes
3, 4
3, 6
–
–
–
–
–
–
–
–
–
1
2
4
5
6
7