LSI53CF92A LSI, LSI53CF92A Datasheet - Page 37

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

2.7.3 Disconnect Reset
2.8 SCAM Capabilities
The disconnect reset is caused by various circumstances that result in
the chip becoming disconnected from the SCSI bus, as follows:
A disconnect reset resets the following subset of the functions reset by
the Soft Reset:
This section defines how SCAM functionality is accommodated within the
LSI53CF92A SCSI protocol chip. The SCAM terminology and
functionality presented within this section is consistent with definitions
provided within the SCAM specification X3T9.2/93-109r5. The SCAM
additions to the LSI53CF92A allow the chip to be a Level 1 or Level 2
SCAM Master or Slave device.
To provide SCAM functionality, SCSI interface chips must be able to control
individual SCSI control and data lines and be able to disable active
negation of signals. The LSI53CF92A uses hardware sequencers to control
all SCSI interface activity. The general strategy for SCAM implementation
in the LSI53CF92A is to provide a low-level SCSI programming mode along
with hardware support for some of the SCAM operations.
SCAM Capabilities
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
The Target Mode Disconnect, Disconnect Sequence, or Terminate
Sequence command is issued to the chip.
The chip is in initiator mode and the SCSI bus changes to the bus
free state.
The Select or Reselect command terminates with a selection
time-out.
Sequencer Mode bits are cleared (target = 0 and initiator = 0).
Initializes
Releases all SCSI signals except RST/.
Resets disconnect, initiator, and target command modules.
Command
register FIFO to empty.
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