LSI53CF92A LSI, LSI53CF92A Datasheet - Page 132

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

Table 6.14
1. Alternate DMA is disabled.
2. DREQ may stay HIGH if the FIFO has room to accept another byte during DMA write, or send
3. DACK/ must toggle once for each access.
4. DBWR/ edges may precede or follow DACK/ edges. Recommended values are: t
6-16
Symbol
another byte during DMA read. If the current DMA acknowledge cycle fills the FIFO (write) or
empties the FIFO (read), then DREQ goes LOW.
If DBWR/ is held LOW, the data setup to DACK/ HIGH is 15 ns minimum; data hold from DACK/
HIGH is 4 ns minimum.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
10
11
12
13
14
1
2
3
4
5
6
7
8
9
Parameter
DACK/ LOW to DREQ LOW
DACK/ HIGH to DREQ HIGH
DACK/ HIGH to DACK/ LOW
DACK/ pulse width
DACK/ period (LOW to LOW)
DACK/ period (HIGH to HIGH)
DACK/ LOW to data valid
DACK/ HIGH to data bus disable
DACK/ LOW to DBWR/ LOW
DBWR/ pulse width
DBWR/ HIGH to DACK/ HIGH
Data setup to DBWR/
Data hold from DBWR/
DBWR/ HIGH to DBWR/ LOW
DMA Interface (Nonmultiplexed Mode Only)
Table 6.14
Electrical Specifications
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
lists the DMA Interface, Nonmultiplexed Mode only.
t
t
CP
CP
3 t
3 t
Min
30
30
15
30
–
2
0
0
4
–
CP
CP
+5
+5
Max
1
30
30
30
–
–
–
–
–
–
–
–
–
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
g
0 and t
Notes
3, 4
11
–
–
–
–
–
–
–
–
–
–
2
4
4
0.