LSI53CF92A LSI, LSI53CF92A Datasheet - Page 86

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

4.2 SCAM Register Set
4-36
The following bit descriptions apply when the previous conditions are met.
CFID
RL
Register: 0x0F
Reserved
Register Bank 0
To provide register structures for directly controlling and observing SCSI
bus activity thus providing SCAM functionality, an additional addressing
mode was created for the LSI53CF92A to allow access to the new
registers. This is because the original address map for the LSI53CF92A
was limited to 16 registers and only two read only addresses were
available. The address map is extended to 24 locations through a bank-
select mechanism whereby two sets of registers are mapped to
addresses 0x08–0x0F. The control bit for selecting the SCAM Register
Set is bit 3 in the
either register bank. The complete register map including SCAM
registers is shown in
Registers
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
7
x
x
Chip Family ID
These bits identify the chip family, and are currently fixed
at 0b10010.
Chip Revision Level
These bits identify the current revision level of the chip,
and are currently set to 0x96.
Configuration 4 (Config 4)
Table 4.2
x
x
and in
R
Appendix A, “Register Map.”
x
register, and is visible in
x
x
[7:3]
[2:0]
0
x